bart/FPGC6

mirror of https://github.com/bartpleiter/FPGC6

Author	SHA1 Message	Date
bart	28bcde6466 New SDRAM controller that uses both SDRAM chips. Now separate bus from MU for better performance, as controller runs at 100MHz. Also updated some debug code as debugging was needed. Tested working in hardware. 2x performance boost in some cases.	1 year ago
bart	1026f4776c Cleaned up some files	2 years ago
bart	1cf78e1fab Added and updated the assembler (python version)	2 years ago