 Bart
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a76e895a39
Started working on the CPU pipeline. Basic load, arith and jumps seem to work now. No hazard handling yet.
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2 years ago |
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Bart
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7b0a44b7be
Added testbench template with gtkw config
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2 years ago |
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Bart
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43293f6ca4
Deleted some old memory files
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2 years ago |
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Bart
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55f619efae
Initial commit with some empty Verilog template code from FPGC5
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2 years ago |
