 bartpleiter
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9b3e3a5eb7
Initial progress with faster design.
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2 달 전 |
 bart
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207413dd90
Assembler only needs Int: function, fixed position of program lenght. Ported ROM and UART bootloader over from FPGC5. Updated documentation on interrupts. Added resets. Fixed bug in MU. Increased stack size. Tested everything in hardware. Probably some other fixes and things I forgot.
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2 년 전 |
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bart
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baff95d710
Regbank and stack are now placed in BRAM, fixed combinational loop but further testing needed.
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2 년 전 |
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bart
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f5bc168700
Added DataMem to MU via Arbiter, fixed several bugs while doing this. Works with test code, but will most likely still contain bugs in certain cases.
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2 년 전 |
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bart
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0e533922fb
Connected instruction memory to the MU via the arbiter
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2 년 전 |
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bart
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6881f1be1d
Found bug where the next instruction after READ/WRITE is skipped if DataDelay but no InstrDelay
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2 년 전 |
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Bart
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fb0e4b363f
Instruction memory can now have a delay without messing up the pipeline
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2 년 전 |
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Bart
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302c69937e
Basic CPU design now done with afaik working hazard detection, forwarding and stalls. Tested in hardware on a EP4CE6 using two SSDisplays and dip switches to view the register content (and see if it matches the simulation). No interrupts yet as this can probably be done at a later stage.
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2 년 전 |
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Bart
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9da01544e7
Jump flush now seems to work. Made simple Quartus project to test in hardware and it seems to work fine there as well
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2 년 전 |
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Bart
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a76e895a39
Started working on the CPU pipeline. Basic load, arith and jumps seem to work now. No hazard handling yet.
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2 년 전 |
