Historie revizí

Autor SHA1 Zpráva Datum
  bartpleiter 9b3e3a5eb7 Initial progress with faster design. před 2 měsíci
  bart 207413dd90 Assembler only needs Int: function, fixed position of program lenght. Ported ROM and UART bootloader over from FPGC5. Updated documentation on interrupts. Added resets. Fixed bug in MU. Increased stack size. Tested everything in hardware. Probably some other fixes and things I forgot. před 2 roky
  bart baff95d710 Regbank and stack are now placed in BRAM, fixed combinational loop but further testing needed. před 2 roky
  bart f5bc168700 Added DataMem to MU via Arbiter, fixed several bugs while doing this. Works with test code, but will most likely still contain bugs in certain cases. před 2 roky
  bart 0e533922fb Connected instruction memory to the MU via the arbiter před 2 roky
  bart 6881f1be1d Found bug where the next instruction after READ/WRITE is skipped if DataDelay but no InstrDelay před 2 roky
  Bart fb0e4b363f Instruction memory can now have a delay without messing up the pipeline před 2 roky
  Bart 302c69937e Basic CPU design now done with afaik working hazard detection, forwarding and stalls. Tested in hardware on a EP4CE6 using two SSDisplays and dip switches to view the register content (and see if it matches the simulation). No interrupts yet as this can probably be done at a later stage. před 2 roky
  Bart 9da01544e7 Jump flush now seems to work. Made simple Quartus project to test in hardware and it seems to work fine there as well před 2 roky
  Bart a76e895a39 Started working on the CPU pipeline. Basic load, arith and jumps seem to work now. No hazard handling yet. před 2 roky