 bart
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9ac6dafd0f
POC texture rendering in raycaster. No code optimization yet so it is very slow.
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il y a 1 an |
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bart
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f746bbd20d
Added movement to raycaster. Speed improvements to raycaster and script to precalculate direction and plane values for rotation, for each degree.
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il y a 1 an |
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bart
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0eba720aeb
Initial working POC of a simple raycaster engine.
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il y a 1 an |
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bart
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69d109e653
Added hardware signed and unsigned integer division and modulo. Created simple integer calculator to test. Updated several programs and BDOS to use new division hardware while keeping software calculation as legacy functions.
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il y a 1 an |
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bart
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f3f3a43044
Added fixed-point signed divider to MU. Integrated into FPCALC.
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il y a 1 an |
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bart
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ddd3d60235
Added Fixed-Point BCC library, including a FPCALC application to test it. MULTFP instruction is added to assembler, and some library functions were added during development.
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il y a 1 an |
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bart
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3af9eecaa9
Added signed fixed point multiplication to ALU.
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il y a 1 an |
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bart
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9294ee0605
Removed unused PLLs from quartus design. Replaced main PLL with Cyclone V PLL.
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il y a 1 an |
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bart
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f78729ea77
Fixed L2 cache state machine issue which was only present in the previous commit.
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il y a 1 an |
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bart
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82a433530c
Reverted L2 cache size to 1024 words for easier debugging.
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il y a 1 an |
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bart
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da2bff2ea2
Removed/disabled NTSC from design, as the tiny HDMI monitor is practically always used. Also greatly increased L2 cache size, although no performance benefits for the relatively small programs I currently use for benchmarking.
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il y a 1 an |
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bart
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2287e54c6b
Integrated valid bits into cache block ram. Reset now iteratively clears the entire cache. Allows for much lower FPGA usage and better timings. Should be able to greatly increase cache size as there is an abundance of BRAM.
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il y a 1 an |
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bart
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2fe0518bb3
Improved interrupt timing/alignment, fixing bug where interrupts are not allowed during the UART bootloader.
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il y a 1 an |
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bart
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52f2819774
Removed leftover ccache instructions from debugging instability problems. Commented out required ccache instructions for when L1I cache returns in the future.
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il y a 1 an |
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bart
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9a285550c0
Updated documentation a bit, added newlines to BENCH, removed wrong comments from L2cache.v
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il y a 1 an |
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bart
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88681ec5d0
New arbiter that further improves performance by removing latency for instruction memory access. Created instability again, which I found to be caused by bad interrupt timings. Fixed by changing the interruptValid wire to use branch_MEM for alignment. I do not know why this fixed all problems as it is very hard to simulate this issue. L1 cache should be possible again!
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il y a 1 an |
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bart
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add43b75da
L2 cache at 100MHz now greatly increases performance. Attempted to create l1i and l1d cache, but becomes unstable and the issue is difficult to similate/replicate. Therefore, all l1 cache is now bypassed and the code can be found in l1cacheUnstable.v. As no l1 cache anymore, I removed some ccache statements to increase performance as this instruction currently does nothing.
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il y a 1 an |
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bart
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5af536210d
Fixed instability by adding clear cache instruction during SPI transfer. No idea why this fixed the issue, as the I/O address range is above the limit for cache to work.
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il y a 1 an |
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bart
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9a6bf3cd52
Improved reset for cache. Disabled l2 cache as it currently reduces performance. Added more CCache instructions to code, although likely not needed. Still instability issues when L1I cache is enabled.
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il y a 1 an |
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bart
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7e81e7fa17
Added files missing from last commit (L1I cache).
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il y a 1 an |
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bart
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3253b1bc2c
Added L1I cache. Added clear cache instruction, which is now added in the UART bootloader and BDOS program loaders. Fixed too fast read part in SPI flasher. Snake userbdos program now sometimes crashes, which needs further investigation.
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il y a 1 an |
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bart
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dfb3bbb48e
Added L1D cache. Currently only works stable when valid bit is set 0 on WRITE. Valid bit 1 after cache miss read works fine for some reason.
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il y a 1 an |
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bart
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b6831c4209
Added L2 cache (no L1 for now) between CPU and SDRAM controller. No noticable performance difference, can likely be optimized further to reduce cache hit latency.
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il y a 1 an |
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bart
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28bcde6466
New SDRAM controller that uses both SDRAM chips. Now separate bus from MU for better performance, as controller runs at 100MHz. Also updated some debug code as debugging was needed. Tested working in hardware. 2x performance boost in some cases.
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il y a 1 an |
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bart
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240770cb51
Progress on asm for bcc with new architecture. Started on SDRAM testbench for new controller.
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il y a 1 an |
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bart
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1a2f5e6c55
Added qws Quartus file.
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il y a 1 an |
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bart
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e1bb01a621
Cleaned and renamed Quartus project.
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il y a 1 an |
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bart
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d602419429
Added support for negative ints in .dw for python assembler.
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il y a 1 an |
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bart
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7e822dcae0
Made assembly for rendering mandelbrot program, with other improvements as well.
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il y a 2 ans |
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bart
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19b70deac8
Added support for signed .dw instructions.
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il y a 2 ans |
