 bart
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69d109e653
Added hardware signed and unsigned integer division and modulo. Created simple integer calculator to test. Updated several programs and BDOS to use new division hardware while keeping software calculation as legacy functions.
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1 年之前 |
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bart
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f3f3a43044
Added fixed-point signed divider to MU. Integrated into FPCALC.
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1 年之前 |
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bart
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9294ee0605
Removed unused PLLs from quartus design. Replaced main PLL with Cyclone V PLL.
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1 年之前 |
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bart
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da2bff2ea2
Removed/disabled NTSC from design, as the tiny HDMI monitor is practically always used. Also greatly increased L2 cache size, although no performance benefits for the relatively small programs I currently use for benchmarking.
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1 年之前 |
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bart
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add43b75da
L2 cache at 100MHz now greatly increases performance. Attempted to create l1i and l1d cache, but becomes unstable and the issue is difficult to similate/replicate. Therefore, all l1 cache is now bypassed and the code can be found in l1cacheUnstable.v. As no l1 cache anymore, I removed some ccache statements to increase performance as this instruction currently does nothing.
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1 年之前 |
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bart
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b6831c4209
Added L2 cache (no L1 for now) between CPU and SDRAM controller. No noticable performance difference, can likely be optimized further to reduce cache hit latency.
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1 年之前 |
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bart
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e1bb01a621
Cleaned and renamed Quartus project.
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1 年之前 |
