bart/FPGC6

mirror of https://github.com/bartpleiter/FPGC6

Author	SHA1 Message	Date
bart	9662964536 Added back scripts for converting to spi.txt. Tested code to run from SPI flash, fixed cycle delay for SPI flash in output latch in MU which caused the bus_q to arrive a cycle later than bus_done.	2 years ago
Bart	43293f6ca4 Deleted some old memory files	2 years ago
Bart	55f619efae Initial commit with some empty Verilog template code from FPGC5	2 years ago