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bart
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FPGC6
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https://github.com/bartpleiter/FPGC6
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7cfd77a292
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EP4CE15
cpu100mhz
fast-cpu-pipeline
main
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bart
5af536210d
Fixed instability by adding clear cache instruction during SPI transfer. No idea why this fixed the issue, as the I/O address range is above the limit for cache to work.
hai 1 ano