 bart
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2287e54c6b
Integrated valid bits into cache block ram. Reset now iteratively clears the entire cache. Allows for much lower FPGA usage and better timings. Should be able to greatly increase cache size as there is an abundance of BRAM.
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1 rok pred |
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bart
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2fe0518bb3
Improved interrupt timing/alignment, fixing bug where interrupts are not allowed during the UART bootloader.
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1 rok pred |
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bart
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52f2819774
Removed leftover ccache instructions from debugging instability problems. Commented out required ccache instructions for when L1I cache returns in the future.
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1 rok pred |
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bart
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9a285550c0
Updated documentation a bit, added newlines to BENCH, removed wrong comments from L2cache.v
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1 rok pred |
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bart
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88681ec5d0
New arbiter that further improves performance by removing latency for instruction memory access. Created instability again, which I found to be caused by bad interrupt timings. Fixed by changing the interruptValid wire to use branch_MEM for alignment. I do not know why this fixed all problems as it is very hard to simulate this issue. L1 cache should be possible again!
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1 rok pred |
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bart
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add43b75da
L2 cache at 100MHz now greatly increases performance. Attempted to create l1i and l1d cache, but becomes unstable and the issue is difficult to similate/replicate. Therefore, all l1 cache is now bypassed and the code can be found in l1cacheUnstable.v. As no l1 cache anymore, I removed some ccache statements to increase performance as this instruction currently does nothing.
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1 rok pred |
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bart
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5af536210d
Fixed instability by adding clear cache instruction during SPI transfer. No idea why this fixed the issue, as the I/O address range is above the limit for cache to work.
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1 rok pred |
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bart
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9a6bf3cd52
Improved reset for cache. Disabled l2 cache as it currently reduces performance. Added more CCache instructions to code, although likely not needed. Still instability issues when L1I cache is enabled.
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1 rok pred |
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bart
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7e81e7fa17
Added files missing from last commit (L1I cache).
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1 rok pred |
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bart
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3253b1bc2c
Added L1I cache. Added clear cache instruction, which is now added in the UART bootloader and BDOS program loaders. Fixed too fast read part in SPI flasher. Snake userbdos program now sometimes crashes, which needs further investigation.
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1 rok pred |
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bart
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dfb3bbb48e
Added L1D cache. Currently only works stable when valid bit is set 0 on WRITE. Valid bit 1 after cache miss read works fine for some reason.
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1 rok pred |
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bart
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b6831c4209
Added L2 cache (no L1 for now) between CPU and SDRAM controller. No noticable performance difference, can likely be optimized further to reduce cache hit latency.
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1 rok pred |
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bart
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28bcde6466
New SDRAM controller that uses both SDRAM chips. Now separate bus from MU for better performance, as controller runs at 100MHz. Also updated some debug code as debugging was needed. Tested working in hardware. 2x performance boost in some cases.
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1 rok pred |
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bart
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240770cb51
Progress on asm for bcc with new architecture. Started on SDRAM testbench for new controller.
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1 rok pred |
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bart
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1a2f5e6c55
Added qws Quartus file.
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2 rokov pred |
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bart
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e1bb01a621
Cleaned and renamed Quartus project.
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2 rokov pred |
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bart
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d602419429
Added support for negative ints in .dw for python assembler.
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2 rokov pred |
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bart
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7e822dcae0
Made assembly for rendering mandelbrot program, with other improvements as well.
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2 rokov pred |
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bart
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19b70deac8
Added support for signed .dw instructions.
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2 rokov pred |
 Bart
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cf2db3b9cd
Merge pull request #1 from b4rt-dev/PixelEngine
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2 rokov pred |
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bart
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01b9bb8f29
Added signed right shift operation to CPU, assembler, compiler, code and documentation.
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2 rokov pred |
|
bart
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4dd2ff7765
Merged from main.
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2 rokov pred |
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bart
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6e3cd7cd9c
PixelEngine now works in hardware with both HDMI and NTSC. Added pxtest and mandelbrot test programs.
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2 rokov pred |
|
bart
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7b14d2d273
Improved Pixel Engine.
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2 rokov pred |
|
bart
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6dc8fc396f
Added Pixel Engine in simulation.
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2 rokov pred |
|
bart
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442d51ba85
Added images to documentation, HDMI is working without lvds, init of new sdram controller done.
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2 rokov pred |
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bart
|
308cc6a90d
Fixed SDRAM controller by setting phase shift to 180 degrees.
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2 rokov pred |
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bart
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a76905443f
Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work.
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2 rokov pred |
|
b4rt-dev
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8d56c91fea
Added fast (but inaccurate) and accurate (but slow) option for UART flasher.
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2 rokov pred |
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b4rt-dev
|
118fe8b319
Improved new button check in USB keyboard driver of BDOS
|
2 rokov pred |
