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@@ -0,0 +1,172 @@
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+/*
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+* 32-bit multicycle divider
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+*/
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+
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+/*
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+module Divider(
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+ input clk,
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+ input reset,
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+ input start,
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+ input [31:0] data,
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+
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+ output done,
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+ output [31:0] q
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+);
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+*/
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+
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+module Divider #(
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+ parameter WIDTH=32, // width of numbers in bits (integer and fractional)
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+ parameter FBITS=16 // fractional bits within WIDTH
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+ ) (
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+ input clk, // clock
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+ input rst, // reset
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+ input start, // start calculation
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+ input write_a,
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+ output reg busy = 1'b0, // calculation in progress
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+ output reg done = 1'b0, // calculation is complete (high for one tick)
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+ output reg valid = 1'b0, // result is valid
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+ output reg dbz = 1'b0, // divide by zero
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+ output reg ovf = 1'b0, // overflow
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+ input signed [WIDTH-1:0] a_in, // dividend (numerator)
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+ input signed [WIDTH-1:0] b, // divisor (denominator)
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+ output reg signed [WIDTH-1:0] val = 32'd0 // result value: quotient
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+ );
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+
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+
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+ reg signed [WIDTH-1:0] a = 0;
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+
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+ always @(posedge clk)
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+ begin
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+ if (write_a)
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+ begin
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+ a <= a_in;
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+ end
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+
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+ end
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+
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+ localparam WIDTHU = WIDTH - 1; // unsigned widths are 1 bit narrower
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+ localparam FBITSW = (FBITS == 0) ? 1 : FBITS; // avoid negative vector width when FBITS=0
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+ localparam SMALLEST = {1'b1, {WIDTHU{1'b0}}}; // smallest negative number
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+
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+ localparam ITER = WIDTHU + FBITS; // iteration count: unsigned input width + fractional bits
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+ reg [$clog2(ITER):0] i; // iteration counter (allow ITER+1 iterations for rounding)
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+
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+ reg a_sig = 1'b0;
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+ reg b_sig = 1'b0;
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+ reg sig_diff = 1'b0; // signs of inputs and whether different
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+
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+ reg [WIDTHU-1:0] au = 0;
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+ reg [WIDTHU-1:0] bu = 0; // absolute version of inputs (unsigned)
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+
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+ reg [WIDTHU-1:0] quo = 0;
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+ reg [WIDTHU-1:0] quo_next = 0; // intermediate quotients (unsigned)
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+
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+ reg [WIDTHU:0] acc = 0;
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+ reg [WIDTHU:0] acc_next = 0; // accumulator (unsigned but 1 bit wider)
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+
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+ // input signs
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+ always @(*)
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+ begin
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+ a_sig = a[WIDTH-1+:1];
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+ b_sig = b[WIDTH-1+:1];
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+ end
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+
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+ // division algorithm iteration
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+ always @(*)
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+ begin
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+ if (acc >= {1'b0, bu}) begin
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+ acc_next = acc - bu;
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+ {acc_next, quo_next} = {acc_next[WIDTHU-1:0], quo, 1'b1};
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+ end else begin
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+ {acc_next, quo_next} = {acc, quo} << 1;
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+ end
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+ end
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+
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+ // calculation state machine
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+ parameter IDLE = 5'd0;
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+ parameter INIT = 5'd1;
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+ parameter CALC = 5'd2;
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+ parameter ROUND = 5'd3;
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+ parameter SIGN = 5'd4;
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+ parameter DONE = 5'd5;
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+
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+ reg [2:0] state = IDLE;
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+
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+ always @(posedge clk) begin
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+ done <= 0;
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+ case (state)
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+ INIT: begin
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+ state <= CALC;
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+ ovf <= 0;
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+ i <= 0;
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+ {acc, quo} <= {{WIDTHU{1'b0}}, au, 1'b0}; // initialize calculation
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+ end
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+ CALC: begin
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+ if (i == WIDTHU-1 && quo_next[WIDTHU-1:WIDTHU-FBITSW] != 0) begin // overflow
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+ state <= DONE;
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+ busy <= 0;
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+ done <= 1;
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+ ovf <= 1;
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+ end else begin
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+ if (i == ITER-1) state <= ROUND; // calculation complete after next iteration
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+ i <= i + 1;
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+ acc <= acc_next;
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+ quo <= quo_next;
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+ end
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+ end
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+ ROUND: begin // Gaussian rounding
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+ state <= SIGN;
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+ if (quo_next[0] == 1'b1) begin // next digit is 1, so consider rounding
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+ // round up if quotient is odd or remainder is non-zero
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+ if (quo[0] == 1'b1 || acc_next[WIDTHU:1] != 0) quo <= quo + 1;
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+ end
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+ end
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+ SIGN: begin // adjust quotient sign if non-zero and input signs differ
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+ state <= DONE;
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+ if (quo != 0) val <= (sig_diff) ? {1'b1, -quo} : {1'b0, quo};
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+ busy <= 0;
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+ done <= 1;
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+ valid <= 1;
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+ end
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+ DONE: begin
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+ done <= 1;
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+ state <= IDLE;
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+ end
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+ default: begin // IDLE
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+ if (start) begin
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+ valid <= 0;
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+ if (b == 0) begin // divide by zero
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+ state <= DONE;
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+ busy <= 0;
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+ done <= 1;
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+ dbz <= 1;
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+ ovf <= 0;
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+ end else if (a == SMALLEST || b == SMALLEST) begin // overflow
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+ state <= DONE;
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+ busy <= 0;
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+ done <= 1;
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+ dbz <= 0;
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+ ovf <= 1;
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+ end else begin
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+ state <= INIT;
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+ au <= (a_sig) ? -a[WIDTHU-1:0] : a[WIDTHU-1:0]; // register abs(a)
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+ bu <= (b_sig) ? -b[WIDTHU-1:0] : b[WIDTHU-1:0]; // register abs(b)
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+ sig_diff <= (a_sig ^ b_sig); // register input sign difference
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+ busy <= 1;
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+ dbz <= 0;
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+ ovf <= 0;
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+ end
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+ end
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+ end
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+ endcase
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+ if (rst) begin
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+ state <= IDLE;
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+ busy <= 0;
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+ done <= 0;
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+ valid <= 0;
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+ dbz <= 0;
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+ ovf <= 0;
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+ val <= 0;
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+ end
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+ end
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+endmodule
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