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@@ -3,7 +3,7 @@ These are the current specifications of the FPGC6.
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## CPU
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-- 50MHz 5-stage pipelined CPU with option to add L1 cache
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+- 50MHz 5-stage pipelined CPU (cache not fully implemented yet)
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- 32bit instructions
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- 16 32bit registers, of which 15 are General Purpose, R0 is always 0
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- 27bit program counter for a possible address space of 0.5GiB at 32bit
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@@ -11,10 +11,9 @@ These are the current specifications of the FPGC6.
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## GPU
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-- 320x200 at 256 colors Tile-based and bitmap (at 320x240) rendering GPU with selectable HDMI (480P) and NTSC (240P) output
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-- Two layers of 8x8 Tiles of which one layer (background) has horizontal hardware scrolling support
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-- (currently not working anymore) One Sprite layer with support for 64 Sprites. Max 16 Sprites per horizontal line
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-- Bitmap rendering layer allowing for access to each of the 230x240 individual pixels supporting 256 colors
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+- Two layer tile-based render engine at 320x200 with 256 colors, with horizontal hardware scrolling support for one layer
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+- Bitmap render engine at 320x240 with 24bit color (will be changed to 256 colors in the future to save SRAM)
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+- Integer scaled 640x480 HDMI output over 3.3V LVDS transmitters (not the best compatibility with displays/adapters)
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## Memory
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@@ -23,18 +22,18 @@ These are the current specifications of the FPGC6.
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- SPI bus mode @ 25MHz: Accessible as a normal SPI device
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- 64MiB SDRAM @ 100MHz. 32bit addresses. Used as main memory (currently only 32MiB is accessible until memory map is updated)
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- ~16.4KiB VRAM (SRAM) for tile-based rendering. Combination of 32, 8 and 9bit addresses
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-- 75 KiB VRAM (SRAM) for bitmap rendering
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+- 320x240xbitdepth amount of VRAM (SRAM) for bitmap rendering
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- 2KiB internal ROM for the Bootloader. 32bit addresses
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- 4KiB Hardware Stack (SRAM). 32bit addresses, internal to CPU
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-- 4KiB L2 cache (SRAM)
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## I/O
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- Memory mapped I/O
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- 3 One Shot (OS) timers
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-- PS/2 Keyboard support
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+- PS/2 Keyboard support (to be removed in next hardware revision)
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- UART and power over USB
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-- 4 GPI and 4 GPO pins (will become 8 true GPIO pins eventually)
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+- 4 GPI and 4 GPO pins (will become 8 true GPIO pins eventually when needed)
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- I2S DAC for future audio support
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-- 2 USB host ports with FAT(12/16/32) file system support using a CH376T controller over SPI
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+- 2 USB host ports using a CH376T controller over SPI
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- Ethernet using W5500 over SPI
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+- TODO: list all I/O connected on current PCB version
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bartpleiter
