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divider_tb.v 1.6 KB

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  1. /*
  2. * Testbench
  3. * Simulation for divider module
  4. */
  5. // Set timescale
  6. `timescale 1 ns/1 ns
  7. // Includes
  8. // Memory
  9. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/IO/IDivider.v"
  10. // Define testmodule
  11. module divider_tb;
  12. // clock/reset I/O
  13. reg clk = 1'b0;
  14. reg reset = 1'b0;
  15. reg start = 1'b0;
  16. reg write_a = 1'b0;
  17. reg signed_ope = 1'b0;
  18. wire ready;
  19. reg signed [31:0] a = 0;
  20. reg signed [31:0] b = 0;
  21. wire signed [31:0] quotient;
  22. wire signed [31:0] remainder;
  23. IDivider divider(
  24. .clk (clk),
  25. .rst (reset),
  26. .start(start), // start calculation
  27. .write_a(write_a),
  28. .ready (ready),
  29. .flush(1'b0),
  30. .signed_ope(signed_ope), // calculation in progress
  31. .a(a), // dividend (numerator)
  32. .b(b), // divisor (denominator)
  33. .quotient(quotient), // result value: quotient
  34. .remainder(remainder)
  35. );
  36. initial
  37. begin
  38. // dump everything for GTKwave
  39. $dumpfile("/home/bart/Documents/FPGA/FPGC6/Verilog/output/wave.vcd");
  40. $dumpvars;
  41. #10
  42. // startup
  43. repeat(2)
  44. begin
  45. clk = ~clk;
  46. #10 clk = ~clk;
  47. #10;
  48. end
  49. reset = 1;
  50. repeat(2)
  51. begin
  52. clk = ~clk;
  53. #10 clk = ~clk;
  54. #10;
  55. end
  56. reset = 0;
  57. repeat(4)
  58. begin
  59. clk = ~clk;
  60. #10 clk = ~clk;
  61. #10;
  62. end
  63. a = 17;
  64. write_a = 1;
  65. repeat(1)
  66. begin
  67. clk = ~clk;
  68. #10 clk = ~clk;
  69. #10;
  70. end
  71. write_a = 0;
  72. repeat(4)
  73. begin
  74. clk = ~clk;
  75. #10 clk = ~clk;
  76. #10;
  77. end
  78. a = 0;
  79. b = 3;
  80. start = 1;
  81. repeat(64)
  82. begin
  83. clk = ~clk;
  84. #10 clk = ~clk;
  85. #10;
  86. end
  87. #1 $finish;
  88. end
  89. endmodule