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FSX_tb.v 5.1 KB

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  1. /*
  2. * Testbench
  3. * Simulates the FSX GPU
  4. */
  5. //Set timescale
  6. `timescale 1 ns/1 ns
  7. //Include modules
  8. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/GPU/FSX.v"
  9. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/GPU/BGWrenderer.v"
  10. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/GPU/PixelEngine.v"
  11. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/GPU/TimingGenerator.v"
  12. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/GPU/HDMI/RGB2HDMI.v"
  13. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/GPU/HDMI/TMDSenc.v"
  14. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/GPU/HDMI/lvds.v"
  15. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/GPU/HDMI/ddr.v"
  16. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/GPU/NTSC/NTSC.v"
  17. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/GPU/NTSC/PhaseGen.v"
  18. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/GPU/NTSC/RGB332toNTSC.v"
  19. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/GPU/NTSC/RGBtoYPhaseAmpl.v"
  20. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/Memory/VRAM.v"
  21. //Define testmodule
  22. module FSX_tb;
  23. //Clock I/O
  24. reg clkPixel, clkTMDShalf;
  25. reg nreset;
  26. //---------------------------VRAM32---------------------------------
  27. //VRAM32 I/O
  28. wire vram32_gpu_clk;
  29. wire [13:0] vram32_gpu_addr;
  30. wire [31:0] vram32_gpu_d;
  31. wire vram32_gpu_we;
  32. wire [31:0] vram32_gpu_q;
  33. //because FSX will not write to VRAM
  34. assign vram32_gpu_we = 1'b0;
  35. assign vram32_gpu_d = 32'd0;
  36. VRAM #(
  37. .WIDTH(32),
  38. .WORDS(1056),
  39. .ADDR_BITS(14),
  40. .LIST("/home/bart/Documents/FPGA/FPGC6/Verilog/memory/vram32.list")
  41. ) vram32(
  42. //GPU port
  43. .gpu_clk (clkPixel),
  44. .gpu_d (vram32_gpu_d),
  45. .gpu_addr (vram32_gpu_addr),
  46. .gpu_we (vram32_gpu_we),
  47. .gpu_q (vram32_gpu_q)
  48. );
  49. //---------------------------VRAM322--------------------------------
  50. //VRAM322 I/O
  51. wire vram322_gpu_clk;
  52. wire [13:0] vram322_gpu_addr;
  53. wire [31:0] vram322_gpu_d;
  54. wire vram322_gpu_we;
  55. wire [31:0] vram322_gpu_q;
  56. //because FSX will not write to VRAM
  57. assign vram322_gpu_we = 1'b0;
  58. assign vram322_gpu_d = 32'd0;
  59. VRAM #(
  60. .WIDTH(32),
  61. .WORDS(1056),
  62. .ADDR_BITS(14),
  63. .LIST("/home/bart/Documents/FPGA/FPGC6/Verilog/memory/vram32.list")
  64. ) vram322(
  65. //GPU port
  66. .gpu_clk (clkPixel),
  67. .gpu_d (vram322_gpu_d),
  68. .gpu_addr (vram322_gpu_addr),
  69. .gpu_we (vram322_gpu_we),
  70. .gpu_q (vram322_gpu_q)
  71. );
  72. //--------------------------VRAM8--------------------------------
  73. //VRAM8 I/O
  74. wire vram8_gpu_clk;
  75. wire [13:0] vram8_gpu_addr;
  76. wire [7:0] vram8_gpu_d;
  77. wire vram8_gpu_we;
  78. wire [7:0] vram8_gpu_q;
  79. //because FSX will not write to VRAM
  80. assign vram8_gpu_we = 1'b0;
  81. assign vram8_gpu_d = 8'd0;
  82. VRAM #(
  83. .WIDTH(8),
  84. .WORDS(8194),
  85. .ADDR_BITS(14),
  86. .LIST("/home/bart/Documents/FPGA/FPGC6/Verilog/memory/vram8.list")
  87. ) vram8(
  88. //GPU port
  89. .gpu_clk (clkPixel),
  90. .gpu_d (vram8_gpu_d),
  91. .gpu_addr (vram8_gpu_addr),
  92. .gpu_we (vram8_gpu_we),
  93. .gpu_q (vram8_gpu_q)
  94. );
  95. //--------------------------VRAMPX--------------------------------
  96. //VRAMPX I/O
  97. wire vramPX_gpu_clk;
  98. wire [16:0] vramPX_gpu_addr;
  99. wire [7:0] vramPX_gpu_d;
  100. wire vramPX_gpu_we;
  101. wire [7:0] vramPX_gpu_q;
  102. //because FSX will not write to VRAM
  103. assign vramPX_gpu_we = 1'b0;
  104. assign vramPX_gpu_d = 8'd0;
  105. VRAM #(
  106. .WIDTH(8),
  107. .WORDS(76800),
  108. .ADDR_BITS(17),
  109. .LIST("/home/bart/Documents/FPGA/FPGC6/Verilog/memory/vramPX.list")
  110. ) vramPX(
  111. //GPU port
  112. .gpu_clk (clkPixel),
  113. .gpu_d (vramPX_gpu_d),
  114. .gpu_addr (vramPX_gpu_addr),
  115. .gpu_we (vramPX_gpu_we),
  116. .gpu_q (vramPX_gpu_q)
  117. );
  118. //-----------------------FSX-------------------------
  119. //FSX I/O
  120. wire frameDrawn; // interrupt signal for CPU
  121. wire [7:0] composite; // NTSC composite video signal
  122. reg selectOutput; // 1 -> HDMI, 0 -> Composite
  123. // HDMI signals
  124. wire [3:0] TMDS_p;
  125. wire [3:0] TMDS_n;
  126. FSX fsx(
  127. //Clocks
  128. .clkPixel (clkPixel),
  129. .clkTMDShalf (clkTMDShalf),
  130. .clk14 (clkPixel),
  131. .clk114 (clkTMDShalf),
  132. .clkMuxOut (clkPixel),
  133. //HDMI
  134. .TMDS_p (TMDS_p),
  135. .TMDS_n (TMDS_n),
  136. //NTSC composite
  137. .composite (composite),
  138. //Select output method
  139. .selectOutput (selectOutput),
  140. //VRAM32
  141. .vram32_addr (vram32_gpu_addr),
  142. .vram32_q (vram32_gpu_q),
  143. //VRAM32
  144. .vram322_addr (vram322_gpu_addr),
  145. .vram322_q (vram322_gpu_q),
  146. //VRAM8
  147. .vram8_addr (vram8_gpu_addr),
  148. .vram8_q (vram8_gpu_q),
  149. //VRAMpixel
  150. .vramPX_addr (vramPX_gpu_addr),
  151. .vramPX_q (vramPX_gpu_q),
  152. //Interrupt signal
  153. .frameDrawn (frameDrawn)
  154. );
  155. initial
  156. begin
  157. //Dump everything for GTKwave
  158. $dumpfile("/home/bart/Documents/FPGA/FPGC6/Verilog/output/wave.vcd");
  159. $dumpvars;
  160. clkTMDShalf = 0;
  161. clkPixel = 0;
  162. selectOutput = 1;
  163. nreset = 1;
  164. repeat(280000) // 850000 for exactly one frame at 640x480 (1110000 for exactly one frame at 1706x240)
  165. begin
  166. // TMDS: 125MHz, Pixel: 25MHz (320x240 4x wide: TMDS: 165MHz, Pixel: 33MHz)
  167. #4 clkTMDShalf = ~clkTMDShalf;
  168. #4 clkTMDShalf = ~clkTMDShalf;
  169. #4 clkTMDShalf = ~clkTMDShalf;
  170. #4 clkTMDShalf = ~clkTMDShalf;
  171. #4 clkTMDShalf = ~clkTMDShalf; clkPixel = ~clkPixel;
  172. end
  173. #1 $finish;
  174. end
  175. endmodule