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SDRAM.gtkw 1.2 KB

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  1. [*]
  2. [*] GTKWave Analyzer v3.3.107 (w)1999-2020 BSI
  3. [*] Tue Aug 22 13:34:09 2023
  4. [*]
  5. [dumpfile] "/home/bart/Documents/FPGA/FPGC6/Verilog/output/wave.vcd"
  6. [dumpfile_mtime] "Tue Aug 22 11:55:06 2023"
  7. [dumpfile_size] 25820
  8. [savefile] "/home/bart/Documents/FPGA/FPGC6/Verilog/output/SDRAM.gtkw"
  9. [timestart] 1217000
  10. [size] 2560 1387
  11. [pos] -1 -1
  12. *-17.666576 1569000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
  13. [treeopen] SDRAM_tb.
  14. [sst_width] 227
  15. [signals_width] 451
  16. [sst_expanded] 1
  17. [sst_vpaned_height] 410
  18. @28
  19. SDRAM_tb.clk
  20. SDRAM_tb.reset
  21. @200
  22. -
  23. -Bus
  24. @22
  25. SDRAM_tb.sdc_addr[23:0]
  26. SDRAM_tb.sdc_data[31:0]
  27. @28
  28. SDRAM_tb.sdc_we
  29. SDRAM_tb.sdc_start
  30. @200
  31. -
  32. @22
  33. SDRAM_tb.sdc_q[31:0]
  34. @28
  35. SDRAM_tb.sdc_done
  36. @200
  37. -
  38. -SDRAM
  39. @28
  40. SDRAM_tb.SDRAM_CLK
  41. SDRAM_tb.SDRAM_A[12:0]
  42. SDRAM_tb.SDRAM_BA[1:0]
  43. SDRAM_tb.SDRAM_CASn
  44. SDRAM_tb.SDRAM_CKE
  45. SDRAM_tb.SDRAM_CSn
  46. SDRAM_tb.SDRAM_DQM[3:0]
  47. SDRAM_tb.SDRAM_RASn
  48. SDRAM_tb.SDRAM_WEn
  49. @24
  50. SDRAM_tb.SDRAM_DQ[31:0]
  51. @200
  52. -
  53. -Controller
  54. @24
  55. SDRAM_tb.sdramcontroller.state[4:0]
  56. SDRAM_tb.sdramcontroller.startup_counter[15:0]
  57. @25
  58. SDRAM_tb.sdramcontroller.refresh_counter[9:0]
  59. @28
  60. SDRAM_tb.sdramcontroller.is_refreshing
  61. [pattern_trace] 1
  62. [pattern_trace] 0