MemoryUnit.v 28 KB

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  1. /*
  2. * Memory Unit
  3. */
  4. module MemoryUnit(
  5. // Clocks
  6. input clk,
  7. input reset,
  8. // Bus
  9. input [26:0] bus_addr,
  10. input [31:0] bus_data,
  11. input bus_we,
  12. input bus_start,
  13. output [31:0] bus_q,
  14. output reg bus_done = 1'b0,
  15. /********
  16. * MEMORY
  17. ********/
  18. //SPI Flash / SPI0
  19. inout SPIflash_data, SPIflash_q, SPIflash_wp, SPIflash_hold,
  20. output SPIflash_cs,
  21. output SPIflash_clk,
  22. //VRAM32 cpu port
  23. output [31:0] VRAM32_cpu_d,
  24. output [13:0] VRAM32_cpu_addr,
  25. output VRAM32_cpu_we,
  26. input [31:0] VRAM32_cpu_q,
  27. //VRAM8 cpu port
  28. output [7:0] VRAM8_cpu_d,
  29. output [13:0] VRAM8_cpu_addr,
  30. output VRAM8_cpu_we,
  31. input [7:0] VRAM8_cpu_q,
  32. //VRAMspr cpu port
  33. output [8:0] VRAMspr_cpu_d,
  34. output [13:0] VRAMspr_cpu_addr,
  35. output VRAMspr_cpu_we,
  36. input [8:0] VRAMspr_cpu_q,
  37. //VRAMpx cpu port
  38. output [23:0] VRAMpx_cpu_d,
  39. output [16:0] VRAMpx_cpu_addr,
  40. output VRAMpx_cpu_we,
  41. input [23:0] VRAMpx_cpu_q,
  42. //ROM
  43. output [8:0] ROM_addr,
  44. input [31:0] ROM_q,
  45. /********
  46. * I/O
  47. ********/
  48. //UART0 (Main USB)
  49. input UART0_in,
  50. output UART0_out,
  51. output UART0_rx_interrupt,
  52. //UART1 (APU) DEPRECATED
  53. //input UART1_in,
  54. //output UART1_out,
  55. //output UART1_rx_interrupt,
  56. //UART2 (GP)
  57. input UART2_in,
  58. output UART2_out,
  59. output UART2_rx_interrupt,
  60. //SPI0 (Flash)
  61. //declared under MEMORY
  62. output SPI0_QSPI,
  63. //SPI1 (USB0/CH376T)
  64. output SPI1_clk,
  65. output reg SPI1_cs = 1'b1,
  66. output SPI1_mosi,
  67. input SPI1_miso,
  68. input SPI1_nint,
  69. //SPI2 (USB1/CH376T)
  70. output SPI2_clk,
  71. output reg SPI2_cs = 1'b1,
  72. output SPI2_mosi,
  73. input SPI2_miso,
  74. input SPI2_nint,
  75. //SPI3 (W5500)
  76. output SPI3_clk,
  77. output reg SPI3_cs = 1'b1,
  78. output SPI3_mosi,
  79. input SPI3_miso,
  80. input SPI3_int,
  81. //SPI4 (EXT/GP)
  82. output SPI4_clk,
  83. output reg SPI4_cs = 1'b1,
  84. output SPI4_mosi,
  85. input SPI4_miso,
  86. input SPI4_GP,
  87. //GPIO (Separated GPI and GPO until GPIO module is implemented)
  88. input [3:0] GPI,
  89. output reg [3:0]GPO = 4'd0,
  90. //OStimers
  91. output OST1_int,
  92. output OST2_int,
  93. output OST3_int,
  94. //PS/2
  95. input PS2_clk, PS2_data,
  96. output PS2_int, //Scan code ready signal
  97. output reg halfRes = 1'b0,
  98. //Boot mode
  99. input boot_mode
  100. );
  101. // Address select parameters
  102. localparam
  103. A_SDRAM = 0,
  104. A_FLASH = 1,
  105. A_VRAM32 = 2,
  106. A_VRAM8 = 3,
  107. A_VRAMSPR = 4,
  108. A_ROM = 5,
  109. A_UART0RX = 6,
  110. A_UART0TX = 7,
  111. //A_UART1RX = 8,
  112. //A_UART1TX = 9,
  113. A_UART2RX = 10,
  114. A_UART2TX = 11,
  115. A_SPI0 = 12,
  116. A_SPI0CS = 13,
  117. A_SPI0EN = 14,
  118. A_SPI1 = 15,
  119. A_SPI1CS = 16,
  120. A_SPI1NINT = 17,
  121. A_SPI2 = 18,
  122. A_SPI2CS = 19,
  123. A_SPI2NINT = 20,
  124. A_SPI3 = 21,
  125. A_SPI3CS = 22,
  126. A_SPI3INT = 23,
  127. A_SPI4 = 24,
  128. A_SPI4CS = 25,
  129. A_SPI4GP = 26,
  130. A_GPIO = 27,
  131. A_GPIODIR = 28,
  132. A_TIMER1VAL = 29,
  133. A_TIMER1CTRL = 30,
  134. A_TIMER2VAL = 31,
  135. A_TIMER2CTRL = 32,
  136. A_TIMER3VAL = 33,
  137. A_TIMER3CTRL = 34,
  138. //A_SNESPAD = 35,
  139. A_PS2 = 36,
  140. A_BOOTMODE = 37,
  141. A_VRAMPX = 38,
  142. A_FPDIVWA = 39,
  143. A_FPDIVSTART = 40,
  144. A_IDIVWA = 41,
  145. A_IDIVSTARTS = 42,
  146. A_IDIVSTARTU = 43,
  147. A_IDIVMODS = 44,
  148. A_IDIVMODU = 45,
  149. A_HALFRES = 46,
  150. A_MILLIS = 47;
  151. //------------
  152. //SPI0 (flash) TODO: move this to a separate module
  153. //------------
  154. //SPIreader
  155. wire [23:0] SPIflashReader_addr; //address of flash (32 bit)
  156. wire SPIflashReader_start; //start signal for SPIreader
  157. wire SPIflashReader_cs; //cs
  158. wire [31:0] SPIflashReader_q; //data out
  159. wire SPIflashReader_initDone; //initdone of SPIreader
  160. wire SPIflashReader_recvDone; //recvdone of SPIreader TODO might change this to busy
  161. wire SPIflashReader_reset; //reset SPIreader
  162. wire SPIflashReader_write; //output mode of inout pins (high when writing to SPI flash)
  163. wire SPIflashReader_clk; //clk for spi flash
  164. wire io0_out, io1_out, io2_out, io3_out; //d, q wp, hold output
  165. wire io0_in, io1_in, io2_in, io3_in; //d, q wp, hold input
  166. SPIreader sreader (
  167. .clk (clk),
  168. .reset (SPIflashReader_reset),
  169. .cs (SPIflashReader_cs),
  170. .address (SPIflashReader_addr),
  171. .instr (SPIflashReader_q),
  172. .start (SPIflashReader_start),
  173. .initDone (SPIflashReader_initDone),
  174. .recvDone (SPIflashReader_recvDone),
  175. .write (SPIflashReader_write),
  176. .spi_clk (SPIflashReader_clk),
  177. .io0_out (io0_out),
  178. .io1_out (io1_out),
  179. .io2_out (io2_out),
  180. .io3_out (io3_out),
  181. .io0_in (io0_in),
  182. .io1_in (io1_in),
  183. .io2_in (io2_in),
  184. .io3_in (io3_in)
  185. );
  186. //SPI0 (flash)
  187. wire SPI0_clk;
  188. wire SPI0_mosi;
  189. reg SPI0_cs = 1'b1;
  190. reg SPI0_enable = 1'b0; //high enables SPI0 and disables SPIreader
  191. wire SPI0_start;
  192. wire [7:0] SPI0_in;
  193. wire [7:0] SPI0_out;
  194. wire SPI0_done;
  195. assign SPI0_QSPI = ~SPI0_enable;
  196. SimpleSPI #(
  197. .CLKS_PER_HALF_BIT(1))
  198. SPI0(
  199. .clk (clk),
  200. .reset (reset),
  201. .in_byte (SPI0_in),
  202. .start (SPI0_start),
  203. .done (SPI0_done),
  204. .out_byte (SPI0_out),
  205. .spi_clk (SPI0_clk),
  206. .miso (SPIflash_q),
  207. .mosi (SPI0_mosi)
  208. );
  209. //Tri-state signals
  210. wire SPIcombined_d, SPIcombined_q, SPIcombined_wp, SPIcombined_hold, SPIcombined_OutputEnable;
  211. assign SPIflash_clk = (SPI0_enable) ? SPI0_clk : SPIflashReader_clk;
  212. assign SPIflash_cs = (SPI0_enable) ? SPI0_cs : SPIflashReader_cs;
  213. assign SPIflashReader_reset = (SPI0_enable) ? 1'b1 : reset;
  214. assign SPIcombined_d = (SPI0_enable) ? SPI0_mosi : io0_out;
  215. assign SPIcombined_q = (SPI0_enable) ? 1'bz : io1_out;
  216. assign SPIcombined_wp = (SPI0_enable) ? 1'b1 : io2_out;
  217. assign SPIcombined_hold = (SPI0_enable) ? 1'b1 : io3_out;
  218. assign SPIcombined_OutputEnable = (SPI0_enable) ? 1'b1 : SPIflashReader_write;
  219. assign SPIflash_data = (SPIcombined_OutputEnable) ? SPIcombined_d : 1'bz;
  220. assign SPIflash_q = (SPIcombined_OutputEnable) ? SPIcombined_q : 1'bz;
  221. assign SPIflash_wp = (SPIcombined_OutputEnable) ? SPIcombined_wp : 1'bz;
  222. assign SPIflash_hold = (SPIcombined_OutputEnable) ? SPIcombined_hold : 1'bz;
  223. assign io0_in = (~SPIcombined_OutputEnable) ? SPIflash_data : 1'bz;
  224. assign io1_in = (~SPIcombined_OutputEnable) ? SPIflash_q : 1'bz;
  225. assign io2_in = (~SPIcombined_OutputEnable) ? SPIflash_wp : 1'bz;
  226. assign io3_in = (~SPIcombined_OutputEnable) ? SPIflash_hold : 1'bz;
  227. //------------
  228. //UART0
  229. //------------
  230. wire UART0_r_Tx_DV, UART0_w_Tx_Done;
  231. wire [7:0] UART0_r_Tx_Byte;
  232. UARTtx UART0_tx(
  233. .i_Clock (clk),
  234. .reset (reset),
  235. .i_Tx_DV (UART0_r_Tx_DV),
  236. .i_Tx_Byte (UART0_r_Tx_Byte),
  237. .o_Tx_Active(),
  238. .o_Tx_Serial(UART0_out),
  239. .o_Tx_Done (UART0_w_Tx_Done)
  240. );
  241. wire [7:0] UART0_w_Rx_Byte;
  242. UARTrx UART0_rx(
  243. .i_Clock (clk),
  244. .reset (reset),
  245. .i_Rx_Serial(UART0_in),
  246. .o_Rx_DV (UART0_rx_interrupt),
  247. .o_Rx_Byte (UART0_w_Rx_Byte)
  248. );
  249. //------------
  250. //UART1
  251. //------------
  252. /*
  253. wire UART1_r_Tx_DV, UART1_w_Tx_Done;
  254. wire [7:0] UART1_r_Tx_Byte;
  255. UARTtx UART1_tx(
  256. .i_Clock (clk),
  257. .reset (reset),
  258. .i_Tx_DV (UART1_r_Tx_DV),
  259. .i_Tx_Byte (UART1_r_Tx_Byte),
  260. .o_Tx_Active(),
  261. .o_Tx_Serial(UART1_out),
  262. .o_Tx_Done (UART1_w_Tx_Done)
  263. );
  264. wire [7:0] UART1_w_Rx_Byte;
  265. UARTrx UART1_rx(
  266. .i_Clock (clk),
  267. .reset (reset),
  268. .i_Rx_Serial(UART1_in),
  269. .o_Rx_DV (UART1_rx_interrupt),
  270. .o_Rx_Byte (UART1_w_Rx_Byte)
  271. );
  272. */
  273. //------------
  274. //UART2
  275. //------------
  276. wire UART2_r_Tx_DV, UART2_w_Tx_Done;
  277. wire [7:0] UART2_r_Tx_Byte;
  278. UARTtx UART2_tx(
  279. .i_Clock (clk),
  280. .reset (reset),
  281. .i_Tx_DV (UART2_r_Tx_DV),
  282. .i_Tx_Byte (UART2_r_Tx_Byte),
  283. .o_Tx_Active(),
  284. .o_Tx_Serial(UART2_out),
  285. .o_Tx_Done (UART2_w_Tx_Done)
  286. );
  287. wire [7:0] UART2_w_Rx_Byte;
  288. UARTrx UART2_rx(
  289. .i_Clock (clk),
  290. .reset (reset),
  291. .i_Rx_Serial(UART2_in),
  292. .o_Rx_DV (UART2_rx_interrupt),
  293. .o_Rx_Byte (UART2_w_Rx_Byte)
  294. );
  295. //------------
  296. //SPI1 (CH376T bottom)
  297. //------------
  298. wire SPI1_start;
  299. wire [7:0] SPI1_in;
  300. wire [7:0] SPI1_out;
  301. wire SPI1_done;
  302. SimpleSPI #(
  303. .CLKS_PER_HALF_BIT(2))
  304. SPI1(
  305. .clk (clk),
  306. .reset (reset),
  307. .in_byte (SPI1_in),
  308. .start (SPI1_start),
  309. .done (SPI1_done),
  310. .out_byte (SPI1_out),
  311. .spi_clk (SPI1_clk),
  312. .miso (SPI1_miso),
  313. .mosi (SPI1_mosi)
  314. );
  315. //------------
  316. //SPI2 (CH376T top)
  317. //------------
  318. wire SPI2_start;
  319. wire [7:0] SPI2_in;
  320. wire [7:0] SPI2_out;
  321. wire SPI2_done;
  322. SimpleSPI #(
  323. .CLKS_PER_HALF_BIT(2))
  324. SPI2(
  325. .clk (clk),
  326. .reset (reset),
  327. .in_byte (SPI2_in),
  328. .start (SPI2_start),
  329. .done (SPI2_done),
  330. .out_byte (SPI2_out),
  331. .spi_clk (SPI2_clk),
  332. .miso (SPI2_miso),
  333. .mosi (SPI2_mosi)
  334. );
  335. //------------
  336. //SPI3 (W5500)
  337. //------------
  338. wire SPI3_start;
  339. wire [7:0] SPI3_in;
  340. wire [7:0] SPI3_out;
  341. wire SPI3_done;
  342. SimpleSPI #(
  343. .CLKS_PER_HALF_BIT(1))
  344. SPI3(
  345. .clk (clk),
  346. .reset (reset),
  347. .in_byte (SPI3_in),
  348. .start (SPI3_start),
  349. .done (SPI3_done),
  350. .out_byte (SPI3_out),
  351. .spi_clk (SPI3_clk),
  352. .miso (SPI3_miso),
  353. .mosi (SPI3_mosi)
  354. );
  355. //------------
  356. //SPI4 (EXT/GP)
  357. //------------
  358. wire SPI4_start;
  359. wire [7:0] SPI4_in;
  360. wire [7:0] SPI4_out;
  361. wire SPI4_done;
  362. SimpleSPI #(
  363. .CLKS_PER_HALF_BIT(2))
  364. SPI4(
  365. .clk (clk),
  366. .reset (reset),
  367. .in_byte (SPI4_in),
  368. .start (SPI4_start),
  369. .done (SPI4_done),
  370. .out_byte (SPI4_out),
  371. .spi_clk (SPI4_clk),
  372. .miso (SPI4_miso),
  373. .mosi (SPI4_mosi)
  374. );
  375. //------------
  376. //GPIO
  377. //------------
  378. // TODO: To be implemented
  379. //------------
  380. //OS timer 1
  381. //------------
  382. wire OST1_trigger, OST1_set;
  383. wire [31:0] OST1_value;
  384. OStimer OST1(
  385. .clk (clk),
  386. .reset (reset),
  387. .timerValue (OST1_value),
  388. .setValue (OST1_set),
  389. .trigger (OST1_trigger),
  390. .interrupt (OST1_int)
  391. );
  392. //------------
  393. //OS timer 2
  394. //------------
  395. wire OST2_trigger, OST2_set;
  396. wire [31:0] OST2_value;
  397. OStimer OST2(
  398. .clk (clk),
  399. .reset (reset),
  400. .timerValue (OST2_value),
  401. .setValue (OST2_set),
  402. .trigger (OST2_trigger),
  403. .interrupt (OST2_int)
  404. );
  405. //------------
  406. //OS timer 3
  407. //------------
  408. wire OST3_trigger, OST3_set;
  409. wire [31:0] OST3_value;
  410. OStimer OST3(
  411. .clk (clk),
  412. .reset (reset),
  413. .timerValue (OST3_value),
  414. .setValue (OST3_set),
  415. .trigger (OST3_trigger),
  416. .interrupt (OST3_int)
  417. );
  418. //------------
  419. //Millis counter
  420. //------------
  421. wire [31:0] millis;
  422. MillisCounter millisCounter(
  423. .clk (clk),
  424. .reset (reset),
  425. .millis (millis)
  426. );
  427. //------------
  428. //SNES controller
  429. //------------
  430. /*
  431. wire [15:0] SNES_state;
  432. wire SNES_done;
  433. wire SNES_start;
  434. NESpadReader npr (
  435. .clk(clk),
  436. .reset(reset),
  437. .nesc(SNES_clk),
  438. .nesl(SNES_latch),
  439. .nesd(SNES_data),
  440. .nesState(SNES_state),
  441. .frame(SNES_start),
  442. .done(SNES_done)
  443. );*/
  444. //------------
  445. //PS/2 keyboard
  446. //------------
  447. wire [7:0] PS2_scanCode;
  448. Keyboard PS2Keyboard (
  449. .clk (clk),
  450. .reset (reset),
  451. .ps2d (PS2_data),
  452. .ps2c (PS2_clk),
  453. .rx_done_tick (PS2_int),
  454. .rx_data (PS2_scanCode)
  455. );
  456. wire [31:0] fpdiv_input;
  457. wire fpdiv_write_a;
  458. wire fpdiv_busy;
  459. wire fpdiv_start;
  460. wire [31:0] fpdiv_val;
  461. FPDivider fpdivider(
  462. .clk (clk),
  463. .rst (reset),
  464. .start (fpdiv_start), // start calculation
  465. .write_a (fpdiv_write_a),
  466. .busy (fpdiv_busy), // calculation in progress
  467. //.done (fpdiv_done), // calculation is complete (high for one tick)
  468. //.valid (valid), // result is valid
  469. //.dbz (dbz), // divide by zero
  470. //.ovf (ovf), // overflow
  471. .a_in (bus_data), // dividend (numerator)
  472. .b (bus_data), // divisor (denominator)
  473. .val (fpdiv_val) // result value: quotient
  474. );
  475. wire [31:0] idiv_input;
  476. wire idiv_write_a;
  477. wire idiv_ready;
  478. wire idiv_start;
  479. wire idiv_signed;
  480. wire [31:0] idiv_q;
  481. wire [31:0] idiv_r;
  482. IDivider idivider(
  483. .clk (clk),
  484. .rst (reset),
  485. .start (idiv_start), // start calculation
  486. .write_a (idiv_write_a),
  487. .ready (idiv_ready), // !calculation in progress
  488. .flush (1'b0),
  489. .signed_ope (idiv_signed), // signed or unsiged
  490. .a (bus_data), // dividend (numerator)
  491. .b (bus_data), // divisor (denominator)
  492. .quotient (idiv_q), // result value: quotient
  493. .remainder (idiv_r)
  494. );
  495. reg [31:0] bus_d_reg = 32'd0;
  496. //----
  497. //MEMORY
  498. //----
  499. //SPI FLASH MEMORY
  500. assign SPIflashReader_addr = bus_addr - 27'h800000;
  501. assign SPIflashReader_start = bus_addr >= 27'h800000 && bus_addr < 27'hC00000 && bus_start;
  502. //VRAM32
  503. assign VRAM32_cpu_addr = bus_addr - 27'hC00000;
  504. assign VRAM32_cpu_d = bus_d_reg;
  505. assign VRAM32_cpu_we = bus_addr >= 27'hC00000 && bus_addr < 27'hC00420 && bus_we;
  506. //VRAM8
  507. assign VRAM8_cpu_addr = bus_addr - 27'hC00420;
  508. assign VRAM8_cpu_d = bus_data;
  509. assign VRAM8_cpu_we = bus_addr >= 27'hC00420 && bus_addr < 27'hC02422 && bus_we;
  510. //VRAMspr
  511. assign VRAMspr_cpu_addr = bus_addr - 27'hC02422;
  512. assign VRAMspr_cpu_d = bus_data;
  513. assign VRAMspr_cpu_we = bus_addr >= 27'hC02422 && bus_addr < 27'hC02522 && bus_we;
  514. //VRAMpx
  515. assign VRAMpx_cpu_addr = bus_addr - 27'hD00000;
  516. assign VRAMpx_cpu_d = bus_data;
  517. assign VRAMpx_cpu_we = bus_addr >= 27'hD00000 && bus_addr < 27'hD12C00 && bus_we;
  518. //ROM
  519. assign ROM_addr = bus_addr - 27'hC02522;
  520. //----
  521. //I/O
  522. //----
  523. //UART
  524. assign UART0_r_Tx_DV = bus_addr == 27'hC02723 && bus_we && bus_start;
  525. assign UART0_r_Tx_Byte = bus_data;
  526. //assign UART1_r_Tx_DV = bus_addr == 27'hC02725 && bus_we && bus_start;
  527. //assign UART1_r_Tx_Byte = bus_data;
  528. assign UART2_r_Tx_DV = bus_addr == 27'hC02727 && bus_we && bus_start;
  529. assign UART2_r_Tx_Byte = bus_data;
  530. //SPI
  531. assign SPI0_in = bus_data;
  532. assign SPI0_start = bus_addr == 27'hC02728 && bus_we && bus_start;
  533. assign SPI1_in = bus_data;
  534. assign SPI1_start = bus_addr == 27'hC0272B && bus_we && bus_start;
  535. assign SPI2_in = bus_data;
  536. assign SPI2_start = bus_addr == 27'hC0272E && bus_we && bus_start;
  537. assign SPI3_in = bus_data;
  538. assign SPI3_start = bus_addr == 27'hC02731 && bus_we && bus_start;
  539. assign SPI4_in = bus_data;
  540. assign SPI4_start = bus_addr == 27'hC02734 && bus_we && bus_start;
  541. //OS Timers
  542. assign OST1_value = bus_data;
  543. assign OST1_set = (bus_addr == 27'hC02739 && bus_we);
  544. assign OST1_trigger = (bus_addr == 27'hC0273A && bus_we);
  545. assign OST2_value = bus_data;
  546. assign OST2_set = (bus_addr == 27'hC0273B && bus_we);
  547. assign OST2_trigger = (bus_addr == 27'hC0273C && bus_we);
  548. assign OST3_value = bus_data;
  549. assign OST3_set = (bus_addr == 27'hC0273D && bus_we);
  550. assign OST3_trigger = (bus_addr == 27'hC0273E && bus_we);
  551. //SNES
  552. //assign SNES_start = bus_addr == 27'hC0273F && bus_start;
  553. //Divider
  554. assign fpdiv_write_a = (bus_addr == 27'hC02742 && bus_we);
  555. assign fpdiv_start = (bus_addr == 27'hC02743 && bus_we);
  556. assign idiv_write_a = (bus_addr == 27'hC02744 && bus_we);
  557. assign idiv_start = (
  558. (bus_addr == 27'hC02745 ||
  559. bus_addr == 27'hC02746 ||
  560. bus_addr == 27'hC02747 ||
  561. bus_addr == 27'hC02748
  562. )
  563. && bus_we
  564. );
  565. assign idiv_signed = ((bus_addr == 27'hC02745 || bus_addr == 27'hC02747) && bus_we);
  566. reg [5:0] a_sel;
  567. // Address selection
  568. always @(bus_addr)
  569. begin
  570. a_sel = 6'd0;
  571. if (bus_addr < 27'h800000) a_sel = A_SDRAM;
  572. if (bus_addr >= 27'h800000 && bus_addr < 27'hC00000) a_sel = A_FLASH;
  573. if (bus_addr >= 27'hC00000 && bus_addr < 27'hC00420) a_sel = A_VRAM32;
  574. if (bus_addr >= 27'hC00420 && bus_addr < 27'hC02422) a_sel = A_VRAM8;
  575. if (bus_addr >= 27'hC02422 && bus_addr < 27'hC02522) a_sel = A_VRAMSPR;
  576. if (bus_addr >= 27'hC02522 && bus_addr < 27'hC02722) a_sel = A_ROM;
  577. if (bus_addr == 27'hC02722) a_sel = A_UART0RX;
  578. if (bus_addr == 27'hC02723) a_sel = A_UART0TX;
  579. //if (bus_addr == 27'hC02724) a_sel = A_UART1RX;
  580. //if (bus_addr == 27'hC02725) a_sel = A_UART1TX;
  581. if (bus_addr == 27'hC02726) a_sel = A_UART2RX;
  582. if (bus_addr == 27'hC02727) a_sel = A_UART2TX;
  583. if (bus_addr == 27'hC02728) a_sel = A_SPI0;
  584. if (bus_addr == 27'hC02729) a_sel = A_SPI0CS;
  585. if (bus_addr == 27'hC0272A) a_sel = A_SPI0EN;
  586. if (bus_addr == 27'hC0272B) a_sel = A_SPI1;
  587. if (bus_addr == 27'hC0272C) a_sel = A_SPI1CS;
  588. if (bus_addr == 27'hC0272D) a_sel = A_SPI1NINT;
  589. if (bus_addr == 27'hC0272E) a_sel = A_SPI2;
  590. if (bus_addr == 27'hC0272F) a_sel = A_SPI2CS;
  591. if (bus_addr == 27'hC02730) a_sel = A_SPI2NINT;
  592. if (bus_addr == 27'hC02731) a_sel = A_SPI3;
  593. if (bus_addr == 27'hC02732) a_sel = A_SPI3CS;
  594. if (bus_addr == 27'hC02733) a_sel = A_SPI3INT;
  595. if (bus_addr == 27'hC02734) a_sel = A_SPI4;
  596. if (bus_addr == 27'hC02735) a_sel = A_SPI4CS;
  597. if (bus_addr == 27'hC02736) a_sel = A_SPI4GP;
  598. if (bus_addr == 27'hC02737) a_sel = A_GPIO;
  599. if (bus_addr == 27'hC02738) a_sel = A_GPIODIR;
  600. if (bus_addr == 27'hC02739) a_sel = A_TIMER1VAL;
  601. if (bus_addr == 27'hC0273A) a_sel = A_TIMER1CTRL;
  602. if (bus_addr == 27'hC0273B) a_sel = A_TIMER2VAL;
  603. if (bus_addr == 27'hC0273C) a_sel = A_TIMER2CTRL;
  604. if (bus_addr == 27'hC0273D) a_sel = A_TIMER3VAL;
  605. if (bus_addr == 27'hC0273E) a_sel = A_TIMER3CTRL;
  606. //if (bus_addr == 27'hC0273F) a_sel = A_SNESPAD;
  607. if (bus_addr == 27'hC02740) a_sel = A_PS2;
  608. if (bus_addr == 27'hC02741) a_sel = A_BOOTMODE;
  609. if (bus_addr == 27'hC02742) a_sel = A_FPDIVWA;
  610. if (bus_addr == 27'hC02743) a_sel = A_FPDIVSTART;
  611. if (bus_addr == 27'hC02744) a_sel = A_IDIVWA;
  612. if (bus_addr == 27'hC02745) a_sel = A_IDIVSTARTS;
  613. if (bus_addr == 27'hC02746) a_sel = A_IDIVSTARTU;
  614. if (bus_addr == 27'hC02747) a_sel = A_IDIVMODS;
  615. if (bus_addr == 27'hC02748) a_sel = A_IDIVMODU;
  616. if (bus_addr == 27'hC02749) a_sel = A_HALFRES;
  617. if (bus_addr == 27'hC0274A) a_sel = A_MILLIS;
  618. if (bus_addr >= 27'hD00000 && bus_addr < 27'hD12C00) a_sel = A_VRAMPX;
  619. end
  620. reg [31:0] bus_q_wire;
  621. reg [31:0] bus_q_wire_reg = 32'd0;
  622. always @(*)
  623. begin
  624. case (a_sel)
  625. A_SDRAM: bus_q_wire = 32'd0; //sd_q; sdram is removed now!
  626. A_FLASH: bus_q_wire = SPIflashReader_q;
  627. A_VRAM32: bus_q_wire = VRAM32_cpu_q;
  628. A_VRAM8: bus_q_wire = VRAM8_cpu_q;
  629. A_VRAMSPR: bus_q_wire = VRAMspr_cpu_q;
  630. A_ROM: bus_q_wire = ROM_q;
  631. A_UART0RX: bus_q_wire = UART0_w_Rx_Byte;
  632. //A_UART0TX: bus_q_wire =
  633. //A_UART1RX: bus_q_wire = UART1_w_Rx_Byte;
  634. //A_UART1TX: bus_q_wire =
  635. A_UART2RX: bus_q_wire = UART2_w_Rx_Byte;
  636. //A_UART2TX: bus_q_wire =
  637. A_SPI0: bus_q_wire = SPI0_out;
  638. A_SPI0CS: bus_q_wire = SPI0_cs;
  639. A_SPI0EN: bus_q_wire = SPI0_enable;
  640. A_SPI1: bus_q_wire = SPI1_out;
  641. A_SPI1CS: bus_q_wire = SPI1_cs;
  642. A_SPI1NINT: bus_q_wire = SPI1_nint;
  643. A_SPI2: bus_q_wire = SPI2_out;
  644. A_SPI2CS: bus_q_wire = SPI2_cs;
  645. A_SPI2NINT: bus_q_wire = SPI2_nint;
  646. A_SPI3: bus_q_wire = SPI3_out;
  647. A_SPI3CS: bus_q_wire = SPI3_cs;
  648. A_SPI3INT: bus_q_wire = SPI3_int;
  649. A_SPI4: bus_q_wire = SPI4_out;
  650. A_SPI4CS: bus_q_wire = SPI4_cs;
  651. A_SPI4GP: bus_q_wire = SPI4_GP;
  652. A_GPIO: bus_q_wire = {24'd0, GPO, GPI};
  653. //A_GPIODIR: bus_q_wire =
  654. //A_TIMER1VAL: bus_q_wire =
  655. //A_TIMER1CTRL: bus_q_wire =
  656. //A_TIMER2VAL: bus_q_wire =
  657. //A_TIMER2CTRL: bus_q_wire =
  658. //A_TIMER3VAL: bus_q_wire =
  659. //A_TIMER3CTRL: bus_q_wire =
  660. //A_SNESPAD: bus_q_wire = {16'd0, SNES_state};
  661. A_PS2: bus_q_wire = {24'd0, PS2_scanCode};
  662. A_BOOTMODE: bus_q_wire = {31'd0, boot_mode};
  663. A_VRAMPX: bus_q_wire = VRAMpx_cpu_q;
  664. A_FPDIVSTART: bus_q_wire = fpdiv_val;
  665. A_IDIVSTARTS: bus_q_wire = idiv_q;
  666. A_IDIVSTARTU: bus_q_wire = idiv_q;
  667. A_IDIVMODS: bus_q_wire = idiv_r;
  668. A_IDIVMODU: bus_q_wire = idiv_r;
  669. A_MILLIS: bus_q_wire = millis;
  670. default: bus_q_wire = 32'd0;
  671. endcase
  672. end
  673. always @(posedge clk)
  674. begin
  675. if (reset)
  676. begin
  677. bus_q_wire_reg <= 32'd0;
  678. bus_d_reg <= 32'd0;
  679. end
  680. else
  681. begin
  682. bus_d_reg <= bus_data; // latch for copy instructions to SRAM/regs
  683. // latch output
  684. if (bus_done || bus_done_next || SPIflashReader_recvDone) // TODO: Should probably add more ready statements here
  685. bus_q_wire_reg <= bus_q_wire;
  686. end
  687. end
  688. reg bus_done_next = 1'b0;
  689. assign bus_q = (a_sel == A_ROM) ? ROM_q: // safe because ROM cannot be the destination of a copy instruction
  690. bus_q_wire_reg;
  691. always @(posedge clk)
  692. begin
  693. if (reset)
  694. begin
  695. GPO <= 4'd0;
  696. SPI0_enable <= 1'b0;
  697. bus_done <= 1'b0;
  698. bus_done_next <= 1'b0;
  699. SPI0_cs <= 1'b1;
  700. SPI1_cs <= 1'b1;
  701. SPI2_cs <= 1'b1;
  702. SPI3_cs <= 1'b1;
  703. SPI4_cs <= 1'b1;
  704. //TODO: add reset
  705. end
  706. else
  707. begin
  708. if (bus_done_next)
  709. begin
  710. bus_done_next <= 1'b0;
  711. bus_done <= 1'b1;
  712. end
  713. else
  714. begin
  715. bus_done <= 1'b0;
  716. end
  717. if (bus_start)
  718. begin
  719. case (a_sel)
  720. A_SDRAM:
  721. begin
  722. bus_done <= 1'b0; // this is to make sure bus_done from MU will never be used when SDRAM access
  723. end
  724. A_FLASH:
  725. begin
  726. if (SPIflashReader_recvDone || SPI0_enable)
  727. bus_done <= 1'b1;
  728. end
  729. A_UART0TX:
  730. begin
  731. if (UART0_w_Tx_Done)
  732. bus_done <= 1'b1;
  733. end
  734. /*
  735. A_UART1TX:
  736. begin
  737. if (UART1_w_Tx_Done)
  738. bus_done <= 1'b1;
  739. end
  740. */
  741. A_UART2TX:
  742. begin
  743. if (UART2_w_Tx_Done)
  744. bus_done <= 1'b1;
  745. end
  746. A_SPI0:
  747. begin
  748. if (SPI0_done)
  749. if (!bus_done_next) bus_done_next <= 1'b1;
  750. end
  751. A_SPI0CS:
  752. begin
  753. if (bus_we)
  754. begin
  755. SPI0_cs <= bus_data[0];
  756. end
  757. if (!bus_done_next) bus_done_next <= 1'b1;
  758. end
  759. A_SPI0EN:
  760. begin
  761. if (bus_we)
  762. begin
  763. SPI0_enable <= bus_data[0];
  764. end
  765. if (!bus_done_next) bus_done_next <= 1'b1;
  766. end
  767. A_SPI1:
  768. begin
  769. if (SPI1_done)
  770. if (!bus_done_next) bus_done_next <= 1'b1;
  771. end
  772. A_SPI1CS:
  773. begin
  774. if (bus_we)
  775. begin
  776. SPI1_cs <= bus_data[0];
  777. end
  778. if (!bus_done_next) bus_done_next <= 1'b1;
  779. end
  780. A_SPI2:
  781. begin
  782. if (SPI2_done)
  783. if (!bus_done_next) bus_done_next <= 1'b1;
  784. end
  785. A_SPI2CS:
  786. begin
  787. if (bus_we)
  788. begin
  789. SPI2_cs <= bus_data[0];
  790. end
  791. if (!bus_done_next) bus_done_next <= 1'b1;
  792. end
  793. A_SPI3:
  794. begin
  795. if (SPI3_done)
  796. if (!bus_done_next) bus_done_next <= 1'b1;
  797. end
  798. A_SPI3CS:
  799. begin
  800. if (bus_we)
  801. begin
  802. SPI3_cs <= bus_data[0];
  803. end
  804. if (!bus_done_next) bus_done_next <= 1'b1;
  805. end
  806. A_SPI4:
  807. begin
  808. if (SPI4_done)
  809. if (!bus_done_next) bus_done_next <= 1'b1;
  810. end
  811. A_SPI4CS:
  812. begin
  813. if (bus_we)
  814. begin
  815. SPI4_cs <= bus_data[0];
  816. end
  817. if (!bus_done_next) bus_done_next <= 1'b1;
  818. end
  819. A_GPIO:
  820. begin
  821. if (bus_we)
  822. begin
  823. GPO <= bus_data[7:4];
  824. end
  825. if (!bus_done_next) bus_done_next <= 1'b1;
  826. end
  827. /*
  828. A_SNESPAD:
  829. begin
  830. if (SNES_done)
  831. bus_done <= 1'b1;
  832. end
  833. */
  834. A_VRAM8, A_VRAM32, A_VRAMSPR, A_VRAMPX:
  835. begin
  836. if (bus_we)
  837. bus_done <= 1'b1;
  838. else
  839. if (!bus_done_next) bus_done_next <= 1'b1;
  840. end
  841. A_ROM:
  842. begin
  843. bus_done <= 1'b1;
  844. end
  845. A_FPDIVSTART:
  846. begin
  847. if (!fpdiv_busy)
  848. if (!bus_done_next) bus_done_next <= 1'b1;
  849. end
  850. A_IDIVSTARTS, A_IDIVSTARTU, A_IDIVMODS, A_IDIVMODU:
  851. begin
  852. if (idiv_ready)
  853. if (!bus_done_next) bus_done_next <= 1'b1;
  854. end
  855. A_HALFRES:
  856. begin
  857. if (bus_we)
  858. begin
  859. halfRes <= bus_data[0];
  860. end
  861. if (!bus_done_next) bus_done_next <= 1'b1;
  862. end
  863. default:
  864. begin
  865. if (!bus_done_next) bus_done_next <= 1'b1;
  866. end
  867. endcase
  868. end
  869. end
  870. end
  871. endmodule