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L1Dcache.v 874 B

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  1. /*
  2. * L1 Data Cache
  3. * Sits between Datamem and arbiter
  4. * Currently skipped because of issues
  5. */
  6. module L1Dcache(
  7. // clock/reset inputs
  8. input clk,
  9. input reset,
  10. input cache_reset,
  11. // CPU bus
  12. input [31:0] l2_addr,
  13. input [31:0] l2_data,
  14. input l2_we,
  15. input l2_start,
  16. output [31:0] l2_q,
  17. output l2_done,
  18. // SDRAM controller bus
  19. output [31:0] sdc_addr,
  20. output [31:0] sdc_data,
  21. output sdc_we,
  22. output sdc_start,
  23. input [31:0] sdc_q,
  24. input sdc_done
  25. );
  26. // passthrough to skip
  27. assign sdc_addr = l2_addr;
  28. assign sdc_data = l2_data;
  29. assign sdc_we = l2_we;
  30. assign sdc_start = l2_start;
  31. assign l2_q = sdc_q;
  32. assign l2_done = sdc_done;
  33. endmodule