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FPGC6.v 17 KB

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  1. /*
  2. * Top level design of the FPGC6
  3. */
  4. module FPGC6(
  5. input clk, //50MHz
  6. input clk_SDRAM, //100MHz
  7. input nreset,
  8. //HDMI
  9. output wire [3:0] TMDS_p,
  10. output wire [3:0] TMDS_n,
  11. //SDRAM
  12. output SDRAM_CLK,
  13. output SDRAM_CSn,
  14. output SDRAM_WEn,
  15. output SDRAM_CASn,
  16. output SDRAM_RASn,
  17. output SDRAM_CKE,
  18. output [12:0] SDRAM_A,
  19. output [1:0] SDRAM_BA,
  20. output [3:0] SDRAM_DQM,
  21. inout [31:0] SDRAM_DQ,
  22. //SPI0 flash
  23. output SPI0_clk,
  24. output SPI0_cs,
  25. inout SPI0_data,
  26. inout SPI0_q,
  27. inout SPI0_wp,
  28. inout SPI0_hold,
  29. //SPI1 CH376 bottom
  30. output SPI1_clk,
  31. output SPI1_cs,
  32. output SPI1_mosi,
  33. input SPI1_miso,
  34. input SPI1_nint,
  35. output SPI1_rst,
  36. //SPI2 CH376 top
  37. output SPI2_clk,
  38. output SPI2_cs,
  39. output SPI2_mosi,
  40. input SPI2_miso,
  41. input SPI2_nint,
  42. output SPI2_rst,
  43. //SPI3 W5500
  44. output SPI3_clk,
  45. output SPI3_cs,
  46. output SPI3_mosi,
  47. input SPI3_miso,
  48. input SPI3_int,
  49. output SPI3_nrst,
  50. //SPI4 GP
  51. output SPI4_clk,
  52. output SPI4_cs,
  53. output SPI4_mosi,
  54. input SPI4_miso,
  55. input SPI4_gp,
  56. //UART0
  57. input UART0_in,
  58. output UART0_out,
  59. input UART0_dtr,
  60. //UART1 (currently unused because no UART midi synth anymore)
  61. //input UART1_in,
  62. //output UART1_out,
  63. //UART2
  64. input UART2_in,
  65. output UART2_out,
  66. //PS/2
  67. input PS2_clk, PS2_data,
  68. //Led for debugging
  69. output led,
  70. //GPIO
  71. input [3:0] GPI,
  72. output [3:0] GPO,
  73. //DIP switch
  74. input [3:0] DIPS,
  75. //I2S audio
  76. output I2S_SDIN, I2S_SCLK, I2S_LRCLK, I2S_MCLK,
  77. //Status leds
  78. output led_Booted, led_Eth, led_Flash, led_USB0, led_USB1, led_PS2, led_HDMI, led_QSPI, led_GPU, led_I2S
  79. );
  80. // TMP FIXES FOR NEW PCB
  81. assign I2S_SDIN = 1'b0;
  82. assign I2S_SCLK = 1'b0;
  83. assign I2S_LRCLK = 1'b0;
  84. assign I2S_MCLK = 1'b0;
  85. //-------------------CLK-------------------------
  86. //In hardware a PLL should be used here
  87. // to create the clk and crt_clk
  88. //assign crt_clk = clk; //'fix' for simulation
  89. //Run VGA at CRT speed
  90. //assign vga_clk = crt_clk;
  91. wire clkTMDShalf; // TMDS clock (pre-DDR), 5x pixel clock
  92. wire clkPixel; // Pixel clock
  93. wire clk14; // NTSC clock
  94. wire clk114; // NTSC color clock
  95. wire clkMuxOut; // HDMI or NTSC clock, depending on selectOutput
  96. // everything at clk speed for simulation
  97. assign clkTMDShalf = clk;
  98. assign clkPixel = clk;
  99. assign clk14 = clk;
  100. assign clk114 = clk;
  101. assign clkMuxOut = clk;
  102. //Run SDRAM at 100MHz
  103. assign SDRAM_CLK = clk_SDRAM;
  104. //--------------------Reset&Stabilizers-----------------------
  105. //Reset signals
  106. wire nreset_stable, UART0_dtr_stable, reset;
  107. //Dip switch
  108. wire boot_mode_stable;
  109. //GPU: High when frame just rendered (needs to be stabilized)
  110. wire frameDrawn, frameDrawn_stable;
  111. //Stabilized SPI interrupt signals
  112. wire SPI1_nint_stable, SPI2_nint_stable, SPI3_int_stable, SPI4_gp_stable;
  113. MultiStabilizer multistabilizer (
  114. .clk(clk),
  115. .u0(nreset),
  116. .s0(nreset_stable),
  117. .u1(UART0_dtr),
  118. .s1(UART0_dtr_stable),
  119. .u2(SPI1_nint),
  120. .s2(SPI1_nint_stable),
  121. .u3(SPI2_nint),
  122. .s3(SPI2_nint_stable),
  123. .u4(SPI3_int),
  124. .s4(SPI3_int_stable),
  125. .u5(SPI4_gp),
  126. .s5(SPI4_gp_stable),
  127. .u6(frameDrawn),
  128. .s6(frameDrawn_stable),
  129. .u7(DIPS[0]),
  130. .s7(boot_mode_stable)
  131. );
  132. //Indicator for opened Serial port
  133. assign led = UART0_dtr_stable;
  134. //DRT to reset pulse
  135. wire dtrRst;
  136. DtrReset dtrReset (
  137. .clk(clk),
  138. .dtr(UART0_dtr_stable),
  139. .dtrRst(dtrRst)
  140. );
  141. assign reset = (~nreset_stable) || dtrRst;
  142. //External reset outputs
  143. assign SPI1_rst = reset;
  144. assign SPI2_rst = reset;
  145. assign SPI3_nrst = ~reset;
  146. //---------------------------VRAM32---------------------------------
  147. //VRAM32 I/O
  148. wire vram32_gpu_clk;
  149. wire [13:0] vram32_gpu_addr;
  150. wire [31:0] vram32_gpu_d;
  151. wire vram32_gpu_we;
  152. wire [31:0] vram32_gpu_q;
  153. wire vram32_cpu_clk;
  154. wire [13:0] vram32_cpu_addr;
  155. wire [31:0] vram32_cpu_d;
  156. wire vram32_cpu_we;
  157. wire [31:0] vram32_cpu_q;
  158. //because FSX will not write to VRAM
  159. assign vram32_gpu_we = 1'b0;
  160. assign vram32_gpu_d = 32'd0;
  161. VRAM #(
  162. .WIDTH(32),
  163. .WORDS(1056),
  164. .ADDR_BITS(14),
  165. .LIST("/home/bart/Documents/FPGA/FPGC6/Verilog/memory/vram32.list")
  166. ) vram32(
  167. //CPU port
  168. .cpu_clk (clk),
  169. .cpu_d (vram32_cpu_d),
  170. .cpu_addr (vram32_cpu_addr),
  171. .cpu_we (vram32_cpu_we),
  172. .cpu_q (vram32_cpu_q),
  173. //GPU port
  174. .gpu_clk (clkMuxOut),
  175. .gpu_d (vram32_gpu_d),
  176. .gpu_addr (vram32_gpu_addr),
  177. .gpu_we (vram32_gpu_we),
  178. .gpu_q (vram32_gpu_q)
  179. );
  180. //---------------------------VRAM322--------------------------------
  181. //VRAM322 I/O
  182. wire vram322_gpu_clk;
  183. wire [13:0] vram322_gpu_addr;
  184. wire [31:0] vram322_gpu_d;
  185. wire vram322_gpu_we;
  186. wire [31:0] vram322_gpu_q;
  187. //because FSX will not write to VRAM
  188. assign vram322_gpu_we = 1'b0;
  189. assign vram322_gpu_d = 32'd0;
  190. VRAM #(
  191. .WIDTH(32),
  192. .WORDS(1056),
  193. .ADDR_BITS(14),
  194. .LIST("/home/bart/Documents/FPGA/FPGC6/Verilog/memory/vram32.list")
  195. ) vram322(
  196. //CPU port
  197. .cpu_clk (clk),
  198. .cpu_d (vram32_cpu_d),
  199. .cpu_addr (vram32_cpu_addr),
  200. .cpu_we (vram32_cpu_we),
  201. .cpu_q (),
  202. //GPU port
  203. .gpu_clk (clkMuxOut),
  204. .gpu_d (vram322_gpu_d),
  205. .gpu_addr (vram322_gpu_addr),
  206. .gpu_we (vram322_gpu_we),
  207. .gpu_q (vram322_gpu_q)
  208. );
  209. //--------------------------VRAM8--------------------------------
  210. //VRAM8 I/O
  211. wire vram8_gpu_clk;
  212. wire [13:0] vram8_gpu_addr;
  213. wire [7:0] vram8_gpu_d;
  214. wire vram8_gpu_we;
  215. wire [7:0] vram8_gpu_q;
  216. wire vram8_cpu_clk;
  217. wire [13:0] vram8_cpu_addr;
  218. wire [7:0] vram8_cpu_d;
  219. wire vram8_cpu_we;
  220. wire [7:0] vram8_cpu_q;
  221. //because FSX will not write to VRAM
  222. assign vram8_gpu_we = 1'b0;
  223. assign vram8_gpu_d = 8'd0;
  224. VRAM #(
  225. .WIDTH(8),
  226. .WORDS(8194),
  227. .ADDR_BITS(14),
  228. .LIST("/home/bart/Documents/FPGA/FPGC6/Verilog/memory/vram8.list")
  229. ) vram8(
  230. //CPU port
  231. .cpu_clk (clk),
  232. .cpu_d (vram8_cpu_d),
  233. .cpu_addr (vram8_cpu_addr),
  234. .cpu_we (vram8_cpu_we),
  235. .cpu_q (vram8_cpu_q),
  236. //GPU port
  237. .gpu_clk (clkMuxOut),
  238. .gpu_d (vram8_gpu_d),
  239. .gpu_addr (vram8_gpu_addr),
  240. .gpu_we (vram8_gpu_we),
  241. .gpu_q (vram8_gpu_q)
  242. );
  243. //--------------------------VRAMSPR--------------------------------
  244. //VRAMSPR I/O
  245. wire vramSPR_gpu_clk;
  246. wire [13:0] vramSPR_gpu_addr;
  247. wire [8:0] vramSPR_gpu_d;
  248. wire vramSPR_gpu_we;
  249. wire [8:0] vramSPR_gpu_q;
  250. wire vramSPR_cpu_clk;
  251. wire [13:0] vramSPR_cpu_addr;
  252. wire [8:0] vramSPR_cpu_d;
  253. wire vramSPR_cpu_we;
  254. wire [8:0] vramSPR_cpu_q;
  255. //because FSX will not write to VRAM
  256. assign vramSPR_gpu_we = 1'b0;
  257. assign vramSPR_gpu_d = 9'd0;
  258. VRAM #(
  259. .WIDTH(9),
  260. .WORDS(256),
  261. .ADDR_BITS(14),
  262. .LIST("/home/bart/Documents/FPGA/FPGC6/Verilog/memory/vramSPR.list")
  263. ) vramSPR(
  264. //CPU port
  265. .cpu_clk (clk),
  266. .cpu_d (vramSPR_cpu_d),
  267. .cpu_addr (vramSPR_cpu_addr),
  268. .cpu_we (vramSPR_cpu_we),
  269. .cpu_q (vramSPR_cpu_q),
  270. //GPU port
  271. .gpu_clk (clkMuxOut),
  272. .gpu_d (vramSPR_gpu_d),
  273. .gpu_addr (vramSPR_gpu_addr),
  274. .gpu_we (vramSPR_gpu_we),
  275. .gpu_q (vramSPR_gpu_q)
  276. );
  277. //--------------------------VRAMPX--------------------------------
  278. //VRAMPX I/O
  279. wire vramPX_gpu_clk;
  280. wire [16:0] vramPX_gpu_addr;
  281. wire [23:0] vramPX_gpu_d;
  282. wire vramPX_gpu_we;
  283. wire [23:0] vramPX_gpu_q;
  284. wire vramPX_cpu_clk;
  285. wire [16:0] vramPX_cpu_addr;
  286. wire [23:0] vramPX_cpu_d;
  287. wire vramPX_cpu_we;
  288. wire [23:0] vramPX_cpu_q;
  289. // FSX will not write to VRAM
  290. assign vramPX_gpu_we = 1'b0;
  291. assign vramPX_gpu_d = 24'd0;
  292. VRAM #(
  293. .WIDTH(24),
  294. .WORDS(76800),
  295. .ADDR_BITS(17),
  296. .LIST("memory/vramPX.list")
  297. ) vramPX(
  298. // CPU port
  299. .cpu_clk (clk),
  300. .cpu_d (vramPX_cpu_d),
  301. .cpu_addr (vramPX_cpu_addr),
  302. .cpu_we (vramPX_cpu_we),
  303. .cpu_q (vramPX_cpu_q),
  304. // GPU port
  305. .gpu_clk (clkMuxOut),
  306. .gpu_d (vramPX_gpu_d),
  307. .gpu_addr (vramPX_gpu_addr),
  308. .gpu_we (vramPX_gpu_we),
  309. .gpu_q (vramPX_gpu_q)
  310. );
  311. //-------------------ROM-------------------------
  312. //ROM I/O
  313. wire [8:0] rom_addr;
  314. wire [31:0] rom_q;
  315. ROM rom(
  316. .clk (clk),
  317. .reset (reset),
  318. .address (rom_addr),
  319. .q (rom_q)
  320. );
  321. //----------------SDRAM Controller------------------
  322. // inputs
  323. wire [23:0] sdc_addr; // address to write or to start reading from
  324. wire [31:0] sdc_data; // data to write
  325. wire sdc_we; // write enable
  326. wire sdc_start; // start trigger
  327. // outputs
  328. wire [31:0] sdc_q; // memory output
  329. wire sdc_done; // output ready
  330. SDRAMcontroller sdramcontroller(
  331. // clock/reset inputs
  332. .clk (clk_SDRAM),
  333. .reset (reset),
  334. // interface inputs
  335. .sdc_addr (sdc_addr),
  336. .sdc_data (sdc_data),
  337. .sdc_we (sdc_we),
  338. .sdc_start (sdc_start),
  339. // interface outputs
  340. .sdc_q (sdc_q),
  341. .sdc_done (sdc_done),
  342. // SDRAM signals
  343. .SDRAM_CKE (SDRAM_CKE),
  344. .SDRAM_CSn (SDRAM_CSn),
  345. .SDRAM_WEn (SDRAM_WEn),
  346. .SDRAM_CASn (SDRAM_CASn),
  347. .SDRAM_RASn (SDRAM_RASn),
  348. .SDRAM_A (SDRAM_A),
  349. .SDRAM_BA (SDRAM_BA),
  350. .SDRAM_DQM (SDRAM_DQM),
  351. .SDRAM_DQ (SDRAM_DQ)
  352. );
  353. //-----------------------FSX-------------------------
  354. //FSX I/O
  355. wire [7:0] composite; // NTSC composite video signal
  356. reg selectOutput = 1'b1; // 1 -> HDMI, 0 -> Composite
  357. wire halfRes;
  358. FSX fsx(
  359. //Clocks
  360. .clkPixel (clkPixel),
  361. .clkTMDShalf (clkTMDShalf),
  362. //.clk14 (clk14),
  363. //.clk114 (clk114),
  364. .clkMuxOut (clkMuxOut),
  365. //HDMI
  366. .TMDS_p (TMDS_p),
  367. .TMDS_n (TMDS_n),
  368. //NTSC composite
  369. //.composite (composite),
  370. //Select output method
  371. //.selectOutput (selectOutput),
  372. .halfRes(halfRes),
  373. //VRAM32
  374. .vram32_addr (vram32_gpu_addr),
  375. .vram32_q (vram32_gpu_q),
  376. //VRAM32
  377. .vram322_addr (vram322_gpu_addr),
  378. .vram322_q (vram322_gpu_q),
  379. //VRAM8
  380. .vram8_addr (vram8_gpu_addr),
  381. .vram8_q (vram8_gpu_q),
  382. //VRAMSPR
  383. .vramSPR_addr (vramSPR_gpu_addr),
  384. .vramSPR_q (vramSPR_gpu_q),
  385. //VRAMPX
  386. .vramPX_addr (vramPX_gpu_addr),
  387. .vramPX_q (vramPX_gpu_q),
  388. //Interrupt signal
  389. .frameDrawn (frameDrawn)
  390. );
  391. //----------------Memory Unit--------------------
  392. //Memory Unit I/O
  393. //Bus
  394. wire [26:0] bus_addr;
  395. wire [31:0] bus_data;
  396. wire bus_we;
  397. wire bus_start;
  398. wire [31:0] bus_q;
  399. wire bus_done;
  400. //Interrupt signals
  401. wire OST1_int, OST2_int, OST3_int;
  402. wire UART0_rx_int, UART2_rx_int;
  403. wire PS2_int;
  404. wire SPI0_QSPI;
  405. MemoryUnit mu(
  406. //clock
  407. .clk (clk),
  408. .reset (reset),
  409. //CPU connection (Bus)
  410. .bus_addr (bus_addr),
  411. .bus_data (bus_data),
  412. .bus_we (bus_we),
  413. .bus_start (bus_start),
  414. .bus_q (bus_q),
  415. .bus_done (bus_done),
  416. /********
  417. * MEMORY
  418. ********/
  419. //SPI Flash / SPI0
  420. .SPIflash_data (SPI0_data),
  421. .SPIflash_q (SPI0_q),
  422. .SPIflash_wp (SPI0_wp),
  423. .SPIflash_hold (SPI0_hold),
  424. .SPIflash_cs (SPI0_cs),
  425. .SPIflash_clk (SPI0_clk),
  426. //VRAM32 cpu port
  427. .VRAM32_cpu_d (vram32_cpu_d),
  428. .VRAM32_cpu_addr (vram32_cpu_addr),
  429. .VRAM32_cpu_we (vram32_cpu_we),
  430. .VRAM32_cpu_q (vram32_cpu_q),
  431. //VRAM8 cpu port
  432. .VRAM8_cpu_d (vram8_cpu_d),
  433. .VRAM8_cpu_addr (vram8_cpu_addr),
  434. .VRAM8_cpu_we (vram8_cpu_we),
  435. .VRAM8_cpu_q (vram8_cpu_q),
  436. //VRAMspr cpu port
  437. .VRAMspr_cpu_d (vramSPR_cpu_d),
  438. .VRAMspr_cpu_addr (vramSPR_cpu_addr),
  439. .VRAMspr_cpu_we (vramSPR_cpu_we),
  440. .VRAMspr_cpu_q (vramSPR_cpu_q),
  441. // VRAMpx cpu port
  442. .VRAMpx_cpu_d (vramPX_cpu_d),
  443. .VRAMpx_cpu_addr (vramPX_cpu_addr),
  444. .VRAMpx_cpu_we (vramPX_cpu_we),
  445. .VRAMpx_cpu_q (vramPX_cpu_q),
  446. //ROM
  447. .ROM_addr (rom_addr),
  448. .ROM_q (rom_q),
  449. /********
  450. * I/O
  451. ********/
  452. //UART0 (Main USB)
  453. .UART0_in (UART0_in),
  454. .UART0_out (UART0_out),
  455. .UART0_rx_interrupt (UART0_rx_int),
  456. //UART1 (APU)
  457. /*.UART1_in (),
  458. .UART1_out (),
  459. .UART1_rx_interrupt (),
  460. */
  461. //UART2 (GP)
  462. .UART2_in (UART2_in),
  463. .UART2_out (UART2_out),
  464. .UART2_rx_interrupt (UART2_rx_int),
  465. //SPI0 (Flash)
  466. //declared under MEMORY
  467. .SPI0_QSPI (SPI0_QSPI),
  468. //SPI1 (USB0/CH376T)
  469. .SPI1_clk (SPI1_clk),
  470. .SPI1_cs (SPI1_cs),
  471. .SPI1_mosi (SPI1_mosi),
  472. .SPI1_miso (SPI1_miso),
  473. .SPI1_nint (SPI1_nint_stable),
  474. //SPI2 (USB1/CH376T)
  475. .SPI2_clk (SPI2_clk),
  476. .SPI2_cs (SPI2_cs),
  477. .SPI2_mosi (SPI2_mosi),
  478. .SPI2_miso (SPI2_miso),
  479. .SPI2_nint (SPI2_nint_stable),
  480. //SPI3 (W5500)
  481. .SPI3_clk (SPI3_clk),
  482. .SPI3_cs (SPI3_cs),
  483. .SPI3_mosi (SPI3_mosi),
  484. .SPI3_miso (SPI3_miso),
  485. .SPI3_int (SPI3_int_stable),
  486. //SPI4 (EXT/GP)
  487. .SPI4_clk (SPI4_clk),
  488. .SPI4_cs (SPI4_cs),
  489. .SPI4_mosi (SPI4_mosi),
  490. .SPI4_miso (SPI4_miso),
  491. .SPI4_GP (SPI4_gp_stable),
  492. //GPIO (Separated GPI and GPO until GPIO module is implemented)
  493. .GPI (GPI[3:0]),
  494. .GPO (GPO[3:0]),
  495. //OStimers
  496. .OST1_int (OST1_int),
  497. .OST2_int (OST2_int),
  498. .OST3_int (OST3_int),
  499. //SNESpad
  500. /*
  501. .SNES_clk (),
  502. .SNES_latch (),
  503. .SNES_data (),
  504. */
  505. //PS/2
  506. .PS2_clk (PS2_clk),
  507. .PS2_data (PS2_data),
  508. .PS2_int (PS2_int), //Scan code ready signal
  509. .halfRes(halfRes),
  510. //Boot mode
  511. .boot_mode (boot_mode_stable)
  512. );
  513. //------------L2 Cache--------------
  514. //CPU bus
  515. wire [23:0] l2_addr; // address to write or to start reading from
  516. wire [31:0] l2_data; // data to write
  517. wire l2_we; // write enable
  518. wire l2_start; // start trigger
  519. wire [31:0] l2_q; // memory output
  520. wire l2_done; // output ready
  521. L2cache l2cache(
  522. .clk (clk_SDRAM),
  523. .reset (reset),
  524. // CPU bus
  525. .l2_addr (l2_addr),
  526. .l2_data (l2_data),
  527. .l2_we (l2_we),
  528. .l2_start (l2_start),
  529. .l2_q (l2_q),
  530. .l2_done (l2_done),
  531. // sdram bus
  532. .sdc_addr (sdc_addr),
  533. .sdc_data (sdc_data),
  534. .sdc_we (sdc_we),
  535. .sdc_start (sdc_start),
  536. .sdc_q (sdc_q),
  537. .sdc_done (sdc_done)
  538. );
  539. //---------------CPU----------------
  540. //CPU I/O
  541. wire [26:0] PC;
  542. CPU cpu(
  543. .clk (clk),
  544. .reset (reset),
  545. // bus
  546. .bus_addr (bus_addr),
  547. .bus_data (bus_data),
  548. .bus_we (bus_we),
  549. .bus_start (bus_start),
  550. .bus_q (bus_q),
  551. .bus_done (bus_done),
  552. // sdram bus
  553. .sdc_addr (l2_addr),
  554. .sdc_data (l2_data),
  555. .sdc_we (l2_we),
  556. .sdc_start (l2_start),
  557. .sdc_q (l2_q),
  558. .sdc_done (l2_done),
  559. .int1 (OST1_int), //OStimer1
  560. .int2 (OST2_int), //OStimer2
  561. .int3 (UART0_rx_int), //UART0 rx (MAIN)
  562. .int4 (frameDrawn_stable), //GPU Frame Drawn
  563. .int5 (OST3_int), //OStimer3
  564. .int6 (PS2_int), //PS/2 scancode ready
  565. .int7 (1'b0), //UART1 rx (APU)
  566. .int8 (UART2_rx_int), //UART2 rx (EXT)
  567. .PC (PC)
  568. );
  569. //-----------STATUS LEDS-----------
  570. assign led_Booted = (PC >= 27'hC02522 | reset);
  571. assign led_HDMI = (~selectOutput | reset);
  572. assign led_QSPI = (~SPI0_QSPI | reset);
  573. LEDvisualizer #(.MIN_CLK(100000))
  574. LEDvisUSB0
  575. (
  576. .clk(clk),
  577. .reset(reset),
  578. .activity(~SPI1_cs),
  579. .LED(led_USB0)
  580. );
  581. LEDvisualizer #(.MIN_CLK(100000))
  582. LEDvisUSB1
  583. (
  584. .clk(clk),
  585. .reset(reset),
  586. .activity(~SPI2_cs),
  587. .LED(led_USB1)
  588. );
  589. LEDvisualizer #(.MIN_CLK(100000))
  590. LEDvisEth
  591. (
  592. .clk(clk),
  593. .reset(reset),
  594. .activity(~SPI3_cs),
  595. .LED(led_Eth)
  596. );
  597. LEDvisualizer #(.MIN_CLK(100000))
  598. LEDvisPS2
  599. (
  600. .clk(clk),
  601. .reset(reset),
  602. .activity(PS2_int),
  603. .LED(led_PS2)
  604. );
  605. LEDvisualizer #(.MIN_CLK(100000))
  606. LEDvisFlash
  607. (
  608. .clk(clk),
  609. .reset(reset),
  610. .activity(~SPI0_cs),
  611. .LED(led_Flash)
  612. );
  613. LEDvisualizer #(.MIN_CLK(100000))
  614. LEDvisGPU
  615. (
  616. .clk(clk),
  617. .reset(reset),
  618. .activity(vram32_cpu_we|vram8_cpu_we|vramSPR_cpu_we|vramPX_cpu_we),
  619. .LED(led_GPU)
  620. );
  621. LEDvisualizer #(.MIN_CLK(100000))
  622. LEDvisI2S
  623. (
  624. .clk(clk),
  625. .reset(reset),
  626. .activity(I2S_SDIN),
  627. .LED(led_I2S)
  628. );
  629. endmodule