InstructionDecoder.v 1.3 KB

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  1. /*
  2. * Instruction Decoder
  3. */
  4. module InstructionDecoder(
  5. input [31:0] instr,
  6. output [3:0] instrOP,
  7. output [3:0] aluOP,
  8. output [2:0] branchOP,
  9. output [31:0] constAlu,
  10. output [31:0] constAluu,
  11. output [31:0] const16,
  12. output [15:0] const16u,
  13. output [26:0] const27,
  14. output [3:0] areg, breg, dreg,
  15. output he, oe, sig
  16. );
  17. assign instrOP = instr[31:28];
  18. assign aluOP = instr[27:24];
  19. assign branchOP = instr[3:1];
  20. assign constAlu = {{16{instr[23]}}, instr[23:8]}; // sign extend to 32 bit
  21. assign constAluu = {instr[23:8]};
  22. assign const16 = {{16{instr[27]}}, instr[27:12]}; // sign extend to 32 bit
  23. assign const16u = instr[27:12];
  24. assign const27 = instr[27:1];
  25. // areg is at a different position during an arithc instruction,
  26. // because const16 must be used as inputb for many operations to make sense
  27. // and because of forwarding, breg should then be 0
  28. assign areg = (instrOP == 4'b0001) ? instr[7:4] : instr[11:8];
  29. assign breg = (instrOP == 4'b0001) ? 4'd0 : instr[7:4];
  30. assign dreg = instr[3:0];
  31. assign he = instr[8]; // high-enable (loadhi)
  32. assign oe = instr[0]; // offset-enable (jump[r])
  33. assign sig = instr[0]; // signed comparison (branch)
  34. endmodule