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SDRAMcontroller.v 11 KB

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  1. /*
  2. * SDRAM controller
  3. * Custom made for FPGC with l1 cache (one word per cache line), having two W9825G6KH-6 chips:
  4. * - bus interface to be connected directly to arbiter, so no memory unit in between
  5. * - no burst, so high latency access to single words
  6. */
  7. module SDRAMcontroller(
  8. // clock/reset inputs
  9. input clk,
  10. input reset,
  11. // signal inputs
  12. input [23:0] sdc_addr, // bus_addr
  13. input [31:0] sdc_data, // bus_data
  14. input sdc_we, // bus_we
  15. input sdc_start, // bus_start
  16. // signal outputs
  17. output reg [31:0] sdc_q = 32'd0, // bus_q
  18. output reg sdc_done = 1'b0, // bus_done
  19. // SDRAM signals, initialized for power up
  20. output SDRAM_CSn, SDRAM_WEn, SDRAM_CASn, SDRAM_RASn,
  21. output reg SDRAM_CKE = 1'b1,
  22. output reg [12:0] SDRAM_A = 13'd0,
  23. output reg [1:0] SDRAM_BA = 2'd0,
  24. output reg [3:0] SDRAM_DQM = 4'b1111,
  25. inout [31:0] SDRAM_DQ
  26. );
  27. // SDRAM commands
  28. parameter [3:0] SDRAM_CMD_UNSELECTED= 4'b1000;
  29. parameter [3:0] SDRAM_CMD_NOP = 4'b0111;
  30. parameter [3:0] SDRAM_CMD_ACTIVE = 4'b0011;
  31. parameter [3:0] SDRAM_CMD_READ = 4'b0101;
  32. parameter [3:0] SDRAM_CMD_WRITE = 4'b0100;
  33. parameter [3:0] SDRAM_CMD_BURSTSTOP = 4'b0110;
  34. parameter [3:0] SDRAM_CMD_PRECHARGE = 4'b0010;
  35. parameter [3:0] SDRAM_CMD_REFRESH = 4'b0001;
  36. parameter [3:0] SDRAM_CMD_LOADMODE = 4'b0000;
  37. // Mode register value
  38. // {3'b reserved, 1'b write mode, 1'b reserved, 1'b test mode, 3'b CAS latency, 1'b addressing mode, 3'b burst length}
  39. // CAS latency: 010=2, 011=3
  40. // addressing mode: 0=seq 1=interleave
  41. // burst length: 000=1, 001=2, 010=4, 011=8, 111=full page
  42. parameter [12:0] MODE_REG = {3'b0, 1'b0, 1'b0, 1'b0, 3'b010, 1'b0, 3'b000};
  43. // assign command pins to selected command
  44. reg [3:0] SDRAM_CMD = SDRAM_CMD_NOP; // default to NOP for power up
  45. assign {SDRAM_CSn, SDRAM_RASn, SDRAM_CASn, SDRAM_WEn} = SDRAM_CMD;
  46. // cycles_per_refresh calculation:
  47. // 25MHz -> 25.000.000 cycles per sec
  48. // 25.000.000*0.064 -> 1.600.000 cycles per 64ms
  49. // 1.600.000 / 8192 auto refreshes -> refresh after 196 cycles
  50. // for 50mhz this should be 196*2 cycles and for 100mhz this should be 196*4 cycles
  51. parameter cycles_per_refresh = 784;
  52. reg [9:0] refresh_counter = 10'd0; // cycle counter for refresh command, max 1023
  53. parameter sdram_startup_cycles = 20000; // 200us @ 100MHz -> 20.000 cycles. Lowered for simulation
  54. reg [15:0] startup_counter = 16'd0; // cycle counter for startup, max 65.535
  55. parameter addr_precharge_bit = 10; // address bit that selects which banks are to be precharged (1 == all banks)
  56. // convert input address into row, column and bank
  57. wire [12:0] addr_row;
  58. wire [8:0] addr_col;
  59. wire [1:0] addr_bank;
  60. assign addr_col = sdc_addr[8:0]; // 9 bit columns
  61. assign addr_row = sdc_addr[21:9]; // 13 bit rows
  62. assign addr_bank = sdc_addr[23:22]; // 2 bit banks
  63. // DQ port setup
  64. // write
  65. reg [31:0] SDRAM_DATA = 32'd0;
  66. reg SDRAM_DQ_OE = 1'b0;
  67. assign SDRAM_DQ = SDRAM_DQ_OE ? SDRAM_DATA : 32'hZZZZ;
  68. // read
  69. wire [31:0] SDRAM_Q;
  70. assign SDRAM_Q = SDRAM_DQ;
  71. // state machine
  72. parameter s_init = 5'd0;
  73. parameter s_idle = 5'd1;
  74. parameter s_open_in_2 = 5'd2;
  75. parameter s_open_in_1 = 5'd3;
  76. parameter s_write_1 = 5'd4;
  77. parameter s_write_2 = 5'd5;
  78. parameter s_write_3 = 5'd6;
  79. parameter s_read_1 = 5'd7;
  80. parameter s_read_2 = 5'd8;
  81. parameter s_read_3 = 5'd9;
  82. parameter s_read_4 = 5'd10;
  83. parameter s_write_precharge = 5'd11;
  84. parameter s_idle_in_6 = 5'd12;
  85. parameter s_idle_in_5 = 5'd13;
  86. parameter s_idle_in_4 = 5'd14;
  87. parameter s_idle_in_3 = 5'd15;
  88. parameter s_idle_in_2 = 5'd16;
  89. parameter s_idle_in_1 = 5'd17;
  90. parameter s_read_precharge = 5'd18;
  91. parameter s_read_idle_in_3 = 5'd19;
  92. reg [4:0] state = s_init;
  93. // not used, but useful for debugging
  94. wire refresh = (SDRAM_CMD == SDRAM_CMD_REFRESH);
  95. reg is_refreshing = 1'b0;
  96. always @(posedge clk)
  97. begin
  98. if (reset)
  99. begin
  100. SDRAM_CMD <= SDRAM_CMD_UNSELECTED;
  101. state <= s_init;
  102. startup_counter <= 16'd0;
  103. sdc_done <= 1'b0;
  104. end
  105. else
  106. begin
  107. // default state
  108. SDRAM_CMD <= SDRAM_CMD_NOP;
  109. SDRAM_A <= 13'd0;
  110. SDRAM_BA <= 2'b00;
  111. SDRAM_DQM <= 4'b0000;
  112. sdc_done <= 1'b0;
  113. // update counter for refresh
  114. refresh_counter <= refresh_counter + 1'b1;
  115. case(state)
  116. s_init:
  117. begin
  118. // ~200us pause,
  119. // followed by precharge of all banks,
  120. // followed by two auto refreshes,
  121. // followed by mode register init
  122. SDRAM_CKE <= 1'b1;
  123. // hold DQM high during initial pause
  124. if (startup_counter < sdram_startup_cycles - 50)
  125. begin
  126. SDRAM_DQM <= 4'b1111;
  127. end
  128. case(startup_counter)
  129. (sdram_startup_cycles-50):
  130. begin
  131. // precharge all banks
  132. SDRAM_CMD <= SDRAM_CMD_PRECHARGE;
  133. SDRAM_A[addr_precharge_bit] <= 1'b1; // select all banks
  134. SDRAM_BA <= 2'b00;
  135. end
  136. (sdram_startup_cycles-28):
  137. begin
  138. SDRAM_CMD <= SDRAM_CMD_REFRESH;
  139. end
  140. (sdram_startup_cycles-18):
  141. begin
  142. SDRAM_CMD <= SDRAM_CMD_REFRESH;
  143. end
  144. (sdram_startup_cycles-7):
  145. begin
  146. SDRAM_CMD <= SDRAM_CMD_LOADMODE;
  147. SDRAM_A <= MODE_REG;
  148. end
  149. sdram_startup_cycles:
  150. begin
  151. state <= s_idle;
  152. end
  153. default:
  154. begin
  155. end
  156. endcase
  157. startup_counter <= startup_counter + 1'b1;
  158. end
  159. s_idle_in_6: state <= s_idle_in_5;
  160. s_idle_in_5: state <= s_idle_in_4;
  161. s_idle_in_4: state <= s_idle_in_3;
  162. s_idle_in_3: state <= s_idle_in_2;
  163. s_idle_in_2: state <= s_idle_in_1;
  164. s_idle_in_1: state <= s_idle;
  165. s_idle:
  166. begin
  167. if (refresh_counter > cycles_per_refresh) //refresh has priority!
  168. begin
  169. state <= s_idle_in_6;
  170. is_refreshing <= 1'b1;
  171. SDRAM_CMD <= SDRAM_CMD_REFRESH;
  172. refresh_counter <= 0;
  173. end
  174. else
  175. begin
  176. if (sdc_start)
  177. begin
  178. //--------------------------------
  179. //-- Start the read or write cycle.
  180. //-- First task is to open the row
  181. //--------------------------------
  182. state <= s_open_in_2;
  183. SDRAM_CMD <= SDRAM_CMD_ACTIVE;
  184. SDRAM_A <= addr_row;
  185. SDRAM_BA <= addr_bank;
  186. end
  187. else //if nothing happens, just nop
  188. begin
  189. SDRAM_DQM <= 2'b00;
  190. SDRAM_CMD <= SDRAM_CMD_NOP;
  191. SDRAM_A <= 0;
  192. end
  193. end
  194. end
  195. //--------------------------------------------
  196. //-- Opening the row ready for reads or writes
  197. //--------------------------------------------
  198. s_open_in_2: state <= s_open_in_1;
  199. s_open_in_1:
  200. begin
  201. // if write command
  202. if (sdc_we)
  203. begin
  204. state <= s_write_1;
  205. SDRAM_DATA <= sdc_data; // already present sdram with data
  206. SDRAM_DQ_OE <= 1'b1;
  207. end
  208. else // if read command
  209. begin
  210. state <= s_read_1;
  211. SDRAM_DQ_OE <= 1'b0;
  212. end
  213. end
  214. s_write_1:
  215. begin
  216. state <= s_write_2;
  217. SDRAM_CMD <= SDRAM_CMD_WRITE;
  218. SDRAM_A <= addr_col;
  219. SDRAM_A[addr_precharge_bit] <= 1'b0;
  220. SDRAM_BA <= addr_bank;
  221. SDRAM_DQM <= 2'b00;
  222. SDRAM_DATA <= sdc_data;
  223. end
  224. s_write_2:
  225. begin
  226. state <= s_write_precharge;
  227. SDRAM_DQ_OE <= 1'b0;
  228. sdc_done <= 1'b1; // high for two cycles (this + s_write_precharge)
  229. end
  230. s_write_precharge:
  231. begin
  232. sdc_done <= 1'b1;
  233. state <= s_idle_in_3;
  234. SDRAM_CMD <= SDRAM_CMD_PRECHARGE;
  235. SDRAM_A[addr_precharge_bit] <= 1'b1;
  236. end
  237. //----------------------------------
  238. //-- Processing the read transaction
  239. //----------------------------------
  240. s_read_1:
  241. begin
  242. state <= s_read_2;
  243. SDRAM_CMD <= SDRAM_CMD_READ;
  244. SDRAM_A <= addr_col;
  245. SDRAM_BA <= addr_bank;
  246. SDRAM_A[addr_precharge_bit] <= 1'b0;
  247. SDRAM_DQM <= 2'b00;
  248. end
  249. s_read_2:
  250. begin
  251. state <= s_read_3;
  252. end
  253. s_read_3:
  254. begin
  255. state <= s_read_precharge;
  256. end
  257. s_read_precharge:
  258. begin
  259. sdc_q <= SDRAM_Q;
  260. sdc_done <= 1'b1; // high for two cycles (this + s_read_idle_in_3)
  261. state <= s_read_idle_in_3;
  262. SDRAM_CMD <= SDRAM_CMD_PRECHARGE;
  263. SDRAM_A[addr_precharge_bit] <= 1'b1;
  264. end
  265. s_read_idle_in_3:
  266. begin
  267. sdc_done <= 1'b1;
  268. state <= s_idle_in_2;
  269. end
  270. default:
  271. begin
  272. SDRAM_CMD <= SDRAM_CMD_UNSELECTED;
  273. state <= s_init;
  274. startup_counter <= 16'd0;
  275. end
  276. endcase
  277. end
  278. end
  279. endmodule