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ROM.v 285 B

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  1. /*
  2. * Internal FPGA ROM
  3. * 512x32bits
  4. */
  5. module ROM(
  6. input clk,
  7. input reset,
  8. input [8:0] address,
  9. output reg [31:0] q
  10. );
  11. reg [31:0] rom [0:511];
  12. always @(posedge clk)
  13. begin
  14. q <= rom[address];
  15. end
  16. initial
  17. begin
  18. $readmemb("memory/rom.list", rom);
  19. end
  20. endmodule