RGB2HDMI.v 2.5 KB

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  1. module RGB2HDMI(
  2. input clkTMDS,
  3. input clkRGB,
  4. input [7:0] rRGB,
  5. input [7:0] gRGB,
  6. input [7:0] bRGB,
  7. input blk,
  8. input hs,
  9. input vs,
  10. output wire rTMDS,
  11. output wire rTMDSn,
  12. output wire gTMDS,
  13. output wire gTMDSn,
  14. output wire bTMDS,
  15. output wire bTMDSn,
  16. output wire cTMDS,
  17. output wire cTMDSn
  18. );
  19. wire [9:0] encodedRed;
  20. wire [9:0] encodedGreen;
  21. wire [9:0] encodedBlue;
  22. reg [9:0] latchedRed = 10'd0;
  23. reg [9:0] latchedGreen = 10'd0;
  24. reg [9:0] latchedBlue = 10'd0;
  25. reg [9:0] shiftRed = 10'd0;
  26. reg [9:0] shiftGreen = 10'd0;
  27. reg [9:0] shiftBlue = 10'd0;
  28. reg [9:0] shiftClk = 10'b0000011111;
  29. TMDSenc TMDSr(
  30. .clk (clkRGB),
  31. .data(rRGB),
  32. .c (2'd0),
  33. .blk (blk),
  34. .q (encodedRed)
  35. );
  36. TMDSenc TMDSg(
  37. .clk (clkRGB),
  38. .data(gRGB),
  39. .c (2'd0),
  40. .blk (blk),
  41. .q (encodedGreen)
  42. );
  43. TMDSenc TMDSb(
  44. .clk (clkRGB),
  45. .data(bRGB),
  46. .c ({vs, hs}),
  47. .blk (blk),
  48. .q (encodedBlue)
  49. );
  50. ddr ddrR(
  51. .outclock(clkTMDS),
  52. .datain_h(shiftRed[0]),
  53. .datain_l(shiftRed[1]),
  54. .dataout (rTMDS)
  55. );
  56. ddr ddrG(
  57. .outclock(clkTMDS),
  58. .datain_h(shiftGreen[0]),
  59. .datain_l(shiftGreen[1]),
  60. .dataout (gTMDS)
  61. );
  62. ddr ddrB(
  63. .outclock(clkTMDS),
  64. .datain_h(shiftBlue[0]),
  65. .datain_l(shiftBlue[1]),
  66. .dataout (bTMDS)
  67. );
  68. ddr ddrCLK(
  69. .outclock(clkTMDS),
  70. .datain_h(shiftClk[0]),
  71. .datain_l(shiftClk[1]),
  72. .dataout (cTMDS)
  73. );
  74. ddr ddrRn(
  75. .outclock(clkTMDS),
  76. .datain_h(!shiftRed[0]),
  77. .datain_l(!shiftRed[1]),
  78. .dataout (rTMDSn)
  79. );
  80. ddr ddrGn(
  81. .outclock(clkTMDS),
  82. .datain_h(!shiftGreen[0]),
  83. .datain_l(!shiftGreen[1]),
  84. .dataout (gTMDSn)
  85. );
  86. ddr ddrBn(
  87. .outclock(clkTMDS),
  88. .datain_h(!shiftBlue[0]),
  89. .datain_l(!shiftBlue[1]),
  90. .dataout (bTMDSn)
  91. );
  92. ddr ddrCLKn(
  93. .outclock(clkTMDS),
  94. .datain_h(!shiftClk[0]),
  95. .datain_l(!shiftClk[1]),
  96. .dataout (cTMDSn)
  97. );
  98. always @(posedge clkRGB)
  99. begin
  100. latchedRed <= encodedRed;
  101. latchedGreen <= encodedGreen;
  102. latchedBlue <= encodedBlue;
  103. end
  104. always @(posedge clkTMDS)
  105. begin
  106. if (shiftClk == 10'b0000011111)
  107. begin
  108. shiftRed <= latchedRed;
  109. shiftGreen <= latchedGreen;
  110. shiftBlue <= latchedBlue;
  111. end
  112. else
  113. begin
  114. shiftRed <= {2'b00, shiftRed[9:2]};
  115. shiftGreen <= {2'b00, shiftGreen[9:2]};
  116. shiftBlue <= {2'b00, shiftBlue[9:2]};
  117. end
  118. shiftClk <= {shiftClk[1:0], shiftClk[9:2]};
  119. end
  120. endmodule