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FPGC.v 18 KB

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  1. /*
  2. * Top level design of the FPGC
  3. */
  4. module FPGC(
  5. input clock, //50MHz
  6. input nreset, nBtnl, nBtnr,
  7. //HDMI
  8. output [3:0] TMDS_p,
  9. output [3:0] TMDS_n,
  10. //NTSC composite video signal
  11. output [7:0] composite,
  12. //SDRAM
  13. output SDRAM_CLK,
  14. output SDRAM_CSn,
  15. output SDRAM_WEn,
  16. output SDRAM_CASn,
  17. output SDRAM_RASn,
  18. output SDRAM_CKE,
  19. output [12:0] SDRAM_A,
  20. output [1:0] SDRAM_BA,
  21. output [3:0] SDRAM_DQM,
  22. inout [31:0] SDRAM_DQ,
  23. //SPI0 flash
  24. output SPI0_clk,
  25. output SPI0_cs,
  26. inout SPI0_data,
  27. inout SPI0_q,
  28. inout SPI0_wp,
  29. inout SPI0_hold,
  30. //SPI1 CH376 bottom
  31. output SPI1_clk,
  32. output SPI1_cs,
  33. output SPI1_mosi,
  34. input SPI1_miso,
  35. input SPI1_nint,
  36. output SPI1_rst,
  37. //SPI2 CH376 top
  38. output SPI2_clk,
  39. output SPI2_cs,
  40. output SPI2_mosi,
  41. input SPI2_miso,
  42. input SPI2_nint,
  43. output SPI2_rst,
  44. //SPI3 W5500
  45. output SPI3_clk,
  46. output SPI3_cs,
  47. output SPI3_mosi,
  48. input SPI3_miso,
  49. input SPI3_int,
  50. output SPI3_nrst,
  51. //SPI4 GP
  52. output SPI4_clk,
  53. output SPI4_cs,
  54. output SPI4_mosi,
  55. input SPI4_miso,
  56. input SPI4_gp,
  57. //UART0
  58. input UART0_in,
  59. output UART0_out,
  60. input UART0_dtr,
  61. //UART1 (currently unused because no UART midi synth anymore)
  62. //input UART1_in,
  63. //output UART1_out,
  64. //UART2
  65. input UART2_in,
  66. output UART2_out,
  67. //PS/2
  68. input PS2_clk, PS2_data,
  69. //Led for debugging
  70. output led,
  71. //GPIO
  72. input [3:0] GPI,
  73. output [3:0] GPO,
  74. //DIP switch
  75. input [3:0] DIPS,
  76. //I2S audio
  77. output I2S_SDIN, I2S_SCLK, I2S_LRCLK, I2S_MCLK,
  78. //Status leds
  79. output led_Booted, led_Eth, led_Flash, led_USB0, led_USB1, led_PS2, led_HDMI, led_QSPI, led_GPU, led_I2S
  80. );
  81. // TMP FIXES FOR NEW PCB
  82. assign I2S_SDIN = 1'b0;
  83. assign I2S_SCLK = 1'b0;
  84. assign I2S_LRCLK = 1'b0;
  85. assign I2S_MCLK = 1'b0;
  86. //-------------------CLK-------------------------
  87. // Clock generator PLL
  88. wire clkPixel; // Pixel clock (25MHz)
  89. wire clkTMDShalf; // TMDS clock (pre-DDR), 5x pixel clock (125MHz)
  90. wire clk_SDRAM; // SDRAM clock (100MHz)
  91. wire clk; // System clock (50MHz)
  92. //clock_pll_v clkPll(
  93. //.refclk (clock),
  94. //.outclk_0 (clkPixel),
  95. //.outclk_1 (clkTMDShalf),
  96. //.outclk_2 (clk_SDRAM),
  97. //.outclk_3 (SDRAM_CLK),
  98. //.outclk_4 (clk)
  99. //);
  100. /*
  101. clock_pll clkPll(
  102. .inclk0 (clock),
  103. .areset (1'b0),
  104. .c0 (clk_SDRAM),
  105. .c1 (SDRAM_CLK),
  106. .c2 (clk),
  107. .c3 (clkPixel),
  108. .c4 (clkTMDShalf)
  109. );
  110. */
  111. mainpll mainClkPll(
  112. .refclk (clock),
  113. .rst (1'b0),
  114. .outclk_0 (clk_SDRAM),
  115. .outclk_1 (SDRAM_CLK),
  116. .outclk_2 (clk),
  117. .outclk_3 (clkPixel),
  118. .outclk_4 (clkTMDShalf)
  119. );
  120. wire clk14; //14.31818MHz (50*63/220)
  121. wire clk114; //14.31818 * 8 MHz = 114.5454MHz (50*(63*2)/55)
  122. //NTSC_pll ntscPll(
  123. //.refclk (clock),
  124. //.outclk_0 (clk14),
  125. //.outclk_1 (clk114),
  126. //.outclk_2 (clkPixel), // 25.2MHz dirty fix to allow ALTCLKBUF
  127. //.outclk_3 (clkTMDShalf)
  128. //);
  129. /*
  130. NTSC_pll ntscPll(
  131. .inclk0 (clk),
  132. .areset (1'b0),
  133. //.c0 (clk14),
  134. //.c1 (clk114),
  135. .c2 (clkPixel), // 25.2MHz dirty fix to allow ALTCLKBUF
  136. .c3 (clkTMDShalf)
  137. );
  138. */
  139. wire clkMuxOut;
  140. //wire selectOutput; // 1 -> HDMI, 0 -> Composite
  141. /*
  142. clkMux clkmux(
  143. .inclk0x(clock),
  144. .inclk1x(clock),
  145. .inclk2x(clk14),
  146. .inclk3x(clkPixel),
  147. .clkselect({1'b1, selectOutput}),
  148. .outclk(clkMuxOut)
  149. );
  150. */
  151. assign clkMuxOut = clkPixel;
  152. //--------------------Reset&Stabilizers-----------------------
  153. // Reset signals
  154. wire nreset_stable, UART0_dtr_stable;
  155. wire nreset_unstable;
  156. assign nreset_unstable = nreset & nBtnl & nBtnr;
  157. // Dip switch
  158. wire boot_mode_stable;
  159. // GPU: High when frame just rendered (needs to be stabilized)
  160. wire frameDrawn, frameDrawn_stable;
  161. // Stabilized SPI interrupt signals
  162. wire SPI1_nint_stable, SPI2_nint_stable, SPI3_int_stable, SPI4_gp_stable;
  163. MultiStabilizer multistabilizer(
  164. .clk (clk),
  165. .u0 (nreset_unstable),
  166. .s0 (nreset_stable),
  167. .u1 (UART0_dtr),
  168. .s1 (UART0_dtr_stable),
  169. .u2 (SPI1_nint),
  170. .s2 (SPI1_nint_stable),
  171. .u3 (SPI2_nint),
  172. .s3 (SPI2_nint_stable),
  173. .u4 (SPI3_int),
  174. .s4 (SPI3_int_stable),
  175. .u5 (SPI4_gp),
  176. .s5 (SPI4_gp_stable),
  177. .u6 (frameDrawn),
  178. .s6 (frameDrawn_stable),
  179. .u7 (DIPS[0]),
  180. .s7 (boot_mode_stable)
  181. //.u8 (DIPS[1]),
  182. //.s8 (selectOutput)
  183. );
  184. //assign selectOutput = 1'b0;
  185. // Debug: indicator for opened Serial port
  186. assign led = UART0_dtr_stable;
  187. // DTR to reset pulse
  188. wire dtrRst;
  189. DtrReset dtrReset(
  190. .clk (clk),
  191. .dtr (UART0_dtr_stable),
  192. .dtrRst (dtrRst)
  193. );
  194. wire reset = (~nreset_stable) || dtrRst; // Global reset
  195. // External reset outputs
  196. assign SPI1_rst = reset;
  197. assign SPI2_rst = reset;
  198. assign SPI3_nrst = ~reset;
  199. //---------------------------VRAM32---------------------------------
  200. // VRAM32 I/O
  201. wire vram32_gpu_clk;
  202. wire [13:0] vram32_gpu_addr;
  203. wire [31:0] vram32_gpu_d;
  204. wire vram32_gpu_we;
  205. wire [31:0] vram32_gpu_q;
  206. wire vram32_cpu_clk;
  207. wire [13:0] vram32_cpu_addr;
  208. wire [31:0] vram32_cpu_d;
  209. wire vram32_cpu_we;
  210. wire [31:0] vram32_cpu_q;
  211. // FSX will not write to VRAM
  212. assign vram32_gpu_we = 1'b0;
  213. assign vram32_gpu_d = 32'd0;
  214. VRAM #(
  215. .WIDTH(32),
  216. .WORDS(1056),
  217. .ADDR_BITS(14),
  218. .LIST("memory/vram32.list")
  219. ) vram32(
  220. // CPU port
  221. .cpu_clk (clk),
  222. .cpu_d (vram32_cpu_d),
  223. .cpu_addr (vram32_cpu_addr),
  224. .cpu_we (vram32_cpu_we),
  225. .cpu_q (vram32_cpu_q),
  226. // GPU port
  227. .gpu_clk (clkMuxOut),
  228. .gpu_d (vram32_gpu_d),
  229. .gpu_addr (vram32_gpu_addr),
  230. .gpu_we (vram32_gpu_we),
  231. .gpu_q (vram32_gpu_q)
  232. );
  233. //---------------------------VRAM322--------------------------------
  234. // VRAM322 I/O
  235. wire vram322_gpu_clk;
  236. wire [13:0] vram322_gpu_addr;
  237. wire [31:0] vram322_gpu_d;
  238. wire vram322_gpu_we;
  239. wire [31:0] vram322_gpu_q;
  240. // FSX will not write to VRAM
  241. assign vram322_gpu_we = 1'b0;
  242. assign vram322_gpu_d = 32'd0;
  243. VRAM #(
  244. .WIDTH(32),
  245. .WORDS(1056),
  246. .ADDR_BITS(14),
  247. .LIST("memory/vram32.list")
  248. ) vram322(
  249. // CPU port
  250. .cpu_clk (clk),
  251. .cpu_d (vram32_cpu_d),
  252. .cpu_addr (vram32_cpu_addr),
  253. .cpu_we (vram32_cpu_we),
  254. .cpu_q (),
  255. // GPU port
  256. .gpu_clk (clkMuxOut),
  257. .gpu_d (vram322_gpu_d),
  258. .gpu_addr (vram322_gpu_addr),
  259. .gpu_we (vram322_gpu_we),
  260. .gpu_q (vram322_gpu_q)
  261. );
  262. //--------------------------VRAM8--------------------------------
  263. //VRAM8 I/O
  264. wire vram8_gpu_clk;
  265. wire [13:0] vram8_gpu_addr;
  266. wire [7:0] vram8_gpu_d;
  267. wire vram8_gpu_we;
  268. wire [7:0] vram8_gpu_q;
  269. wire vram8_cpu_clk;
  270. wire [13:0] vram8_cpu_addr;
  271. wire [7:0] vram8_cpu_d;
  272. wire vram8_cpu_we;
  273. wire [7:0] vram8_cpu_q;
  274. // FSX will not write to VRAM
  275. assign vram8_gpu_we = 1'b0;
  276. assign vram8_gpu_d = 8'd0;
  277. VRAM #(
  278. .WIDTH(8),
  279. .WORDS(8194),
  280. .ADDR_BITS(14),
  281. .LIST("memory/vram8.list")
  282. ) vram8(
  283. // CPU port
  284. .cpu_clk (clk),
  285. .cpu_d (vram8_cpu_d),
  286. .cpu_addr (vram8_cpu_addr),
  287. .cpu_we (vram8_cpu_we),
  288. .cpu_q (vram8_cpu_q),
  289. // GPU port
  290. .gpu_clk (clkMuxOut),
  291. .gpu_d (vram8_gpu_d),
  292. .gpu_addr (vram8_gpu_addr),
  293. .gpu_we (vram8_gpu_we),
  294. .gpu_q (vram8_gpu_q)
  295. );
  296. //--------------------------VRAMSPR--------------------------------
  297. //VRAMSPR I/O
  298. wire vramSPR_gpu_clk;
  299. wire [13:0] vramSPR_gpu_addr;
  300. wire [8:0] vramSPR_gpu_d;
  301. wire vramSPR_gpu_we;
  302. wire [8:0] vramSPR_gpu_q;
  303. wire vramSPR_cpu_clk;
  304. wire [13:0] vramSPR_cpu_addr;
  305. wire [8:0] vramSPR_cpu_d;
  306. wire vramSPR_cpu_we;
  307. wire [8:0] vramSPR_cpu_q;
  308. // FSX will not write to VRAM
  309. assign vramSPR_gpu_we = 1'b0;
  310. assign vramSPR_gpu_d = 9'd0;
  311. VRAM #(
  312. .WIDTH(9),
  313. .WORDS(256),
  314. .ADDR_BITS(14),
  315. .LIST("memory/vramSPR.list")
  316. ) vramSPR(
  317. // CPU port
  318. .cpu_clk (clk),
  319. .cpu_d (vramSPR_cpu_d),
  320. .cpu_addr (vramSPR_cpu_addr),
  321. .cpu_we (vramSPR_cpu_we),
  322. .cpu_q (vramSPR_cpu_q),
  323. // GPU port
  324. .gpu_clk (clkMuxOut),
  325. .gpu_d (vramSPR_gpu_d),
  326. .gpu_addr (vramSPR_gpu_addr),
  327. .gpu_we (vramSPR_gpu_we),
  328. .gpu_q (vramSPR_gpu_q)
  329. );
  330. //--------------------------VRAMPX--------------------------------
  331. //VRAMPX I/O
  332. wire vramPX_gpu_clk;
  333. wire [16:0] vramPX_gpu_addr;
  334. wire [23:0] vramPX_gpu_d;
  335. wire vramPX_gpu_we;
  336. wire [23:0] vramPX_gpu_q;
  337. wire vramPX_cpu_clk;
  338. wire [16:0] vramPX_cpu_addr;
  339. wire [23:0] vramPX_cpu_d;
  340. wire vramPX_cpu_we;
  341. wire [23:0] vramPX_cpu_q;
  342. // FSX will not write to VRAM
  343. assign vramPX_gpu_we = 1'b0;
  344. assign vramPX_gpu_d = 24'd0;
  345. VRAM #(
  346. .WIDTH(24),
  347. .WORDS(76800),
  348. .ADDR_BITS(17),
  349. .LIST("memory/vramPX.list")
  350. ) vramPX(
  351. // CPU port
  352. .cpu_clk (clk),
  353. .cpu_d (vramPX_cpu_d),
  354. .cpu_addr (vramPX_cpu_addr),
  355. .cpu_we (vramPX_cpu_we),
  356. .cpu_q (vramPX_cpu_q),
  357. // GPU port
  358. .gpu_clk (clkMuxOut),
  359. .gpu_d (vramPX_gpu_d),
  360. .gpu_addr (vramPX_gpu_addr),
  361. .gpu_we (vramPX_gpu_we),
  362. .gpu_q (vramPX_gpu_q)
  363. );
  364. //-------------------ROM-------------------------
  365. // ROM I/O
  366. wire [8:0] rom_addr;
  367. wire [31:0] rom_q;
  368. ROM rom(
  369. .clk (clk),
  370. .reset (reset),
  371. .address (rom_addr),
  372. .q (rom_q)
  373. );
  374. //----------------SDRAM Controller------------------
  375. // inputs
  376. wire [23:0] sdc_addr; // address to write or to start reading from
  377. wire [31:0] sdc_data; // data to write
  378. wire sdc_we; // write enable
  379. wire sdc_start; // start trigger
  380. // outputs
  381. wire [31:0] sdc_q; // memory output
  382. wire sdc_done; // output ready
  383. SDRAMcontroller sdramcontroller(
  384. // clock/reset inputs
  385. .clk (clk_SDRAM),
  386. .reset (reset),
  387. // interface inputs
  388. .sdc_addr (sdc_addr),
  389. .sdc_data (sdc_data),
  390. .sdc_we (sdc_we),
  391. .sdc_start (sdc_start),
  392. // interface outputs
  393. .sdc_q (sdc_q),
  394. .sdc_done (sdc_done),
  395. // SDRAM signals
  396. .SDRAM_CKE (SDRAM_CKE),
  397. .SDRAM_CSn (SDRAM_CSn),
  398. .SDRAM_WEn (SDRAM_WEn),
  399. .SDRAM_CASn (SDRAM_CASn),
  400. .SDRAM_RASn (SDRAM_RASn),
  401. .SDRAM_A (SDRAM_A),
  402. .SDRAM_BA (SDRAM_BA),
  403. .SDRAM_DQM (SDRAM_DQM),
  404. .SDRAM_DQ (SDRAM_DQ)
  405. );
  406. //-----------------------FSX-------------------------
  407. // FSX I/O
  408. wire halfRes;
  409. //wire [7:0] composite; // NTSC composite video signal
  410. FSX fsx(
  411. // Clocks
  412. .clkPixel (clkPixel),
  413. .clkTMDShalf (clkTMDShalf),
  414. //.clk14 (clk14),
  415. //.clk114 (clk114),
  416. .clkMuxOut (clkMuxOut),
  417. // HDMI
  418. .TMDS_p (TMDS_p),
  419. .TMDS_n (TMDS_n),
  420. // NTSC composite
  421. //.composite (composite),
  422. // Select output method
  423. //.selectOutput (selectOutput),
  424. .halfRes(halfRes),
  425. // VRAM32
  426. .vram32_addr (vram32_gpu_addr),
  427. .vram32_q (vram32_gpu_q),
  428. // VRAM32
  429. .vram322_addr (vram322_gpu_addr),
  430. .vram322_q (vram322_gpu_q),
  431. // VRAM8
  432. .vram8_addr (vram8_gpu_addr),
  433. .vram8_q (vram8_gpu_q),
  434. // VRAMSPR
  435. .vramSPR_addr (vramSPR_gpu_addr),
  436. .vramSPR_q (vramSPR_gpu_q),
  437. //VRAMPX
  438. .vramPX_addr (vramPX_gpu_addr),
  439. .vramPX_q (vramPX_gpu_q),
  440. // Interrupt signal
  441. .frameDrawn (frameDrawn)
  442. );
  443. //----------------Memory Unit--------------------
  444. // Memory Unit I/O
  445. // Bus
  446. wire [26:0] bus_addr;
  447. wire [31:0] bus_data;
  448. wire bus_we;
  449. wire bus_start;
  450. wire [31:0] bus_q;
  451. wire bus_done;
  452. // Interrupt signals
  453. wire OST1_int, OST2_int, OST3_int;
  454. wire UART0_rx_int, UART2_rx_int;
  455. wire PS2_int;
  456. wire SPI0_QSPI;
  457. MemoryUnit mu(
  458. // Clocks
  459. .clk (clk),
  460. .reset (reset),
  461. // Bus
  462. .bus_addr (bus_addr),
  463. .bus_data (bus_data),
  464. .bus_we (bus_we),
  465. .bus_start (bus_start),
  466. .bus_q (bus_q),
  467. .bus_done (bus_done),
  468. /********
  469. * MEMORY
  470. ********/
  471. // SPI Flash / SPI0
  472. .SPIflash_data (SPI0_data),
  473. .SPIflash_q (SPI0_q),
  474. .SPIflash_wp (SPI0_wp),
  475. .SPIflash_hold (SPI0_hold),
  476. .SPIflash_cs (SPI0_cs),
  477. .SPIflash_clk (SPI0_clk),
  478. // VRAM32 cpu port
  479. .VRAM32_cpu_d (vram32_cpu_d),
  480. .VRAM32_cpu_addr (vram32_cpu_addr),
  481. .VRAM32_cpu_we (vram32_cpu_we),
  482. .VRAM32_cpu_q (vram32_cpu_q),
  483. // VRAM8 cpu port
  484. .VRAM8_cpu_d (vram8_cpu_d),
  485. .VRAM8_cpu_addr (vram8_cpu_addr),
  486. .VRAM8_cpu_we (vram8_cpu_we),
  487. .VRAM8_cpu_q (vram8_cpu_q),
  488. // VRAMspr cpu port
  489. .VRAMspr_cpu_d (vramSPR_cpu_d),
  490. .VRAMspr_cpu_addr (vramSPR_cpu_addr),
  491. .VRAMspr_cpu_we (vramSPR_cpu_we),
  492. .VRAMspr_cpu_q (vramSPR_cpu_q),
  493. // VRAMpx cpu port
  494. .VRAMpx_cpu_d (vramPX_cpu_d),
  495. .VRAMpx_cpu_addr (vramPX_cpu_addr),
  496. .VRAMpx_cpu_we (vramPX_cpu_we),
  497. .VRAMpx_cpu_q (vramPX_cpu_q),
  498. // ROM
  499. .ROM_addr (rom_addr),
  500. .ROM_q (rom_q),
  501. /********
  502. * I/O
  503. ********/
  504. // UART0 (Main USB)
  505. .UART0_in (UART0_in),
  506. .UART0_out (UART0_out),
  507. .UART0_rx_interrupt (UART0_rx_int),
  508. // UART1 (APU)
  509. /*
  510. .UART1_in (),
  511. .UART1_out (),
  512. .UART1_rx_interrupt (),
  513. */
  514. // UART2 (GP)
  515. .UART2_in (UART2_in),
  516. .UART2_out (UART2_out),
  517. .UART2_rx_interrupt (UART2_rx_int),
  518. //SPI0 (Flash)
  519. //declared under MEMORY
  520. .SPI0_QSPI (SPI0_QSPI),
  521. // SPI1 (USB0/CH376T, bottom)
  522. .SPI1_clk (SPI1_clk),
  523. .SPI1_cs (SPI1_cs),
  524. .SPI1_mosi (SPI1_mosi),
  525. .SPI1_miso (SPI1_miso),
  526. .SPI1_nint (SPI1_nint_stable),
  527. // SPI2 (USB1/CH376T, top)
  528. .SPI2_clk (SPI2_clk),
  529. .SPI2_cs (SPI2_cs),
  530. .SPI2_mosi (SPI2_mosi),
  531. .SPI2_miso (SPI2_miso),
  532. .SPI2_nint (SPI2_nint_stable),
  533. // SPI3 (W5500)
  534. .SPI3_clk (SPI3_clk),
  535. .SPI3_cs (SPI3_cs),
  536. .SPI3_mosi (SPI3_mosi),
  537. .SPI3_miso (SPI3_miso),
  538. .SPI3_int (SPI3_int_stable),
  539. // SPI4 (EXT/GP)
  540. .SPI4_clk (SPI4_clk),
  541. .SPI4_cs (SPI4_cs),
  542. .SPI4_mosi (SPI4_mosi),
  543. .SPI4_miso (SPI4_miso),
  544. .SPI4_GP (SPI4_gp_stable),
  545. // GPIO (Separated GPI and GPO until GPIO module is implemented)
  546. .GPI (GPI[3:0]),
  547. .GPO (GPO[3:0]),
  548. // OStimers
  549. .OST1_int (OST1_int),
  550. .OST2_int (OST2_int),
  551. .OST3_int (OST3_int),
  552. // SNESpad
  553. /*
  554. .SNES_clk (),
  555. .SNES_latch (),
  556. .SNES_data (),
  557. */
  558. // PS/2
  559. .PS2_clk (PS2_clk),
  560. .PS2_data (PS2_data),
  561. .PS2_int (PS2_int), //Scan code ready signal
  562. .halfRes(halfRes),
  563. // Boot mode
  564. .boot_mode (boot_mode_stable)
  565. );
  566. //------------L2 Cache--------------
  567. //CPU bus
  568. wire [23:0] l2_addr; // address to write or to start reading from
  569. wire [31:0] l2_data; // data to write
  570. wire l2_we; // write enable
  571. wire l2_start; // start trigger
  572. wire [31:0] l2_q; // memory output
  573. wire l2_done; // output ready
  574. L2cache l2cache(
  575. .clk (clk_SDRAM),
  576. .reset (reset),
  577. // CPU bus
  578. .l2_addr (l2_addr),
  579. .l2_data (l2_data),
  580. .l2_we (l2_we),
  581. .l2_start (l2_start),
  582. .l2_q (l2_q),
  583. .l2_done (l2_done),
  584. // sdram bus
  585. .sdc_addr (sdc_addr),
  586. .sdc_data (sdc_data),
  587. .sdc_we (sdc_we),
  588. .sdc_start (sdc_start),
  589. .sdc_q (sdc_q),
  590. .sdc_done (sdc_done)
  591. );
  592. //---------------CPU----------------
  593. // CPU I/O
  594. wire [26:0] PC;
  595. CPU cpu(
  596. // Clock/reset
  597. .clk (clk),
  598. .reset (reset),
  599. .int1 (OST1_int), //OStimer1
  600. .int2 (OST2_int), //OStimer2
  601. .int3 (UART0_rx_int), //UART0 rx (MAIN)
  602. .int4 (frameDrawn_stable), //GPU Frame Drawn
  603. .int5 (OST3_int), //OStimer3
  604. .int6 (PS2_int), //PS/2 scancode ready
  605. .int7 (1'b0), //UART1 rx (APU)
  606. .int8 (UART2_rx_int), //UART2 rx (EXT)
  607. // Bus
  608. .bus_addr (bus_addr),
  609. .bus_data (bus_data),
  610. .bus_we (bus_we),
  611. .bus_start (bus_start),
  612. .bus_q (bus_q),
  613. .bus_done (bus_done),
  614. .PC (PC),
  615. // sdram bus
  616. .sdc_addr (l2_addr),
  617. .sdc_data (l2_data),
  618. .sdc_we (l2_we),
  619. .sdc_start (l2_start),
  620. .sdc_q (l2_q),
  621. .sdc_done (l2_done)
  622. );
  623. //-----------STATUS LEDS-----------
  624. assign led_Booted = (PC >= 27'hC02522 | reset);
  625. assign led_HDMI = 1'b0; //(~selectOutput | reset);
  626. assign led_QSPI = (~SPI0_QSPI | reset);
  627. LEDvisualizer #(.MIN_CLK(100000))
  628. LEDvisUSB0
  629. (
  630. .clk(clk),
  631. .reset(reset),
  632. .activity(~SPI1_cs),
  633. .LED(led_USB0)
  634. );
  635. LEDvisualizer #(.MIN_CLK(100000))
  636. LEDvisUSB1
  637. (
  638. .clk(clk),
  639. .reset(reset),
  640. .activity(~SPI2_cs),
  641. .LED(led_USB1)
  642. );
  643. LEDvisualizer #(.MIN_CLK(100000))
  644. LEDvisEth
  645. (
  646. .clk(clk),
  647. .reset(reset),
  648. .activity(~SPI3_cs),
  649. .LED(led_Eth)
  650. );
  651. LEDvisualizer #(.MIN_CLK(100000))
  652. LEDvisPS2
  653. (
  654. .clk(clk),
  655. .reset(reset),
  656. .activity(PS2_int),
  657. .LED(led_PS2)
  658. );
  659. LEDvisualizer #(.MIN_CLK(100000))
  660. LEDvisFlash
  661. (
  662. .clk(clk),
  663. .reset(reset),
  664. .activity(~SPI0_cs),
  665. .LED(led_Flash)
  666. );
  667. LEDvisualizer #(.MIN_CLK(100000))
  668. LEDvisGPU
  669. (
  670. .clk(clk),
  671. .reset(reset),
  672. .activity(vram32_cpu_we|vram8_cpu_we|vramSPR_cpu_we|vramPX_cpu_we),
  673. .LED(led_GPU)
  674. );
  675. LEDvisualizer #(.MIN_CLK(100000))
  676. LEDvisI2S
  677. (
  678. .clk(clk),
  679. .reset(reset),
  680. .activity(I2S_SDIN),
  681. .LED(led_I2S)
  682. );
  683. endmodule