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Regbank.v 2.3 KB

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  1. /*
  2. * Register Bank
  3. */
  4. module Regbank(
  5. input clk, reset,
  6. input [3:0] addr_a, addr_b,
  7. output [31:0] data_a, data_b,
  8. input [3:0] addr_d,
  9. input [31:0] data_d,
  10. input we, clear, hold
  11. );
  12. reg [31:0] regs [0:15]; // 16 registers of 32 bit, although reg0 is unused
  13. reg [31:0] ramResulta = 32'd0;
  14. reg [31:0] ramResultb = 32'd0;
  15. // RAM logic
  16. always @(posedge clk)
  17. begin
  18. ramResulta <= regs[addr_a];
  19. ramResultb <= regs[addr_b];
  20. if (we && addr_d != 4'd0)
  21. begin
  22. regs[addr_d] <= data_d;
  23. //$display("%d: reg%d := %d", $time, addr_d, data_d);
  24. end
  25. end
  26. reg [31:0] data_a_reg = 32'd0;
  27. reg [31:0] data_b_reg = 32'd0;
  28. reg useRamResult_a = 1'b0;
  29. reg useRamResult_b = 1'b0;
  30. assign data_a = (useRamResult_a) ? ramResulta : data_a_reg;
  31. assign data_b = (useRamResult_b) ? ramResultb : data_b_reg;
  32. // Read
  33. always @(posedge clk)
  34. begin
  35. if (reset)
  36. begin
  37. useRamResult_a <= 1'b0;
  38. useRamResult_b <= 1'b0;
  39. data_a_reg <= 32'd0;
  40. data_b_reg <= 32'd0;
  41. end
  42. else
  43. begin
  44. useRamResult_a <= 1'b0;
  45. useRamResult_b <= 1'b0;
  46. if (clear)
  47. begin
  48. data_a_reg <= 32'd0;
  49. end
  50. else if (hold)
  51. begin
  52. data_a_reg <= data_a_reg;
  53. end
  54. else if (addr_a == 4'd0)
  55. begin
  56. data_a_reg <= 32'd0;
  57. end
  58. else if ((addr_a == addr_d) && we)
  59. begin
  60. data_a_reg <= data_d;
  61. end
  62. else
  63. begin
  64. //data_a <= regs[addr_a];
  65. useRamResult_a <= 1'b1;
  66. end
  67. if (clear)
  68. begin
  69. data_b_reg <= 32'd0;
  70. end
  71. else if (hold)
  72. begin
  73. data_b_reg <= data_b_reg;
  74. end
  75. else if (addr_b == 4'd0)
  76. begin
  77. data_b_reg <= 32'd0;
  78. end
  79. else if ((addr_b == addr_d) && we)
  80. begin
  81. data_b_reg <= data_d;
  82. end
  83. else
  84. begin
  85. //data_b <= regs[addr_b];
  86. useRamResult_b <= 1'b1;
  87. end
  88. end
  89. end
  90. /*
  91. integer i;
  92. initial
  93. begin
  94. for (i = 0; i < 16; i = i + 1)
  95. begin
  96. regs[i] = 32'd0;
  97. end
  98. end
  99. */
  100. endmodule