InstrMem.v 1.0 KB

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  1. /*
  2. * Instruction Memory
  3. */
  4. module InstrMem(
  5. input clk,
  6. input reset,
  7. input [31:0] addr,
  8. output hit,
  9. output [31:0] q,
  10. // bus
  11. output [31:0] bus_addr,
  12. output [31:0] bus_data,
  13. output bus_we,
  14. output bus_start,
  15. input [31:0] bus_q,
  16. input bus_done,
  17. input clear, hold
  18. );
  19. // in case of a clear mid transaction, ignore the next result and start again
  20. reg ignoreNext = 1'b0;
  21. assign hit = bus_done && !ignoreNext;
  22. assign q = (bus_done && !ignoreNext) ? bus_q : 32'd0;
  23. assign bus_addr = addr;
  24. assign bus_data = 32'd0;
  25. assign bus_we = 1'b0;
  26. assign bus_start = !bus_done && !hold;
  27. always @(posedge clk)
  28. begin
  29. if (reset)
  30. begin
  31. ignoreNext <= 1'b0;
  32. end
  33. else
  34. begin
  35. if (ignoreNext)
  36. begin
  37. if (bus_done)
  38. begin
  39. ignoreNext <= 1'b0;
  40. end
  41. end
  42. else if (clear)
  43. begin
  44. if (bus_start)
  45. begin
  46. ignoreNext <= 1'b1;
  47. end
  48. end
  49. end
  50. end
  51. endmodule