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bart
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FPGC6
mirror of https://github.com/bartpleiter/FPGC6
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FPGC6
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Quartus
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mainpll.spd

mainpll.spd 184 B
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  1. <?xml version="1.0" encoding="UTF-8"?>
    2. 

  2. <simPackage>
    3. 

  3.  <file path="mainpll_sim/mainpll.vo" type="VERILOG" />
    4. 

  4.  <topLevel name="mainpll" />
    5. 

  5.  <deviceFamily name="cyclonev" />
    6. 

  6. </simPackage>
    7.