bart 01a00e1603 Update new repo link, add requirements.txt. 2 months ago
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Bootloaders 7e81e7fa17 Added files missing from last commit (L1I cache). 9 months ago
SimTests 28bcde6466 New SDRAM controller that uses both SDRAM chips. Now separate bus from MU for better performance, as controller runs at 100MHz. Also updated some debug code as debugging was needed. Tested working in hardware. 2x performance boost in some cases. 9 months ago
Assembler.py ddd3d60235 Added Fixed-Point BCC library, including a FPCALC application to test it. MULTFP instruction is added to assembler, and some library functions were added during development. 9 months ago
CompileInstruction.py 01a00e1603 Update new repo link, add requirements.txt. 2 months ago
buildToVerilog.sh 28bcde6466 New SDRAM controller that uses both SDRAM chips. Now separate bus from MU for better performance, as controller runs at 100MHz. Also updated some debug code as debugging was needed. Tested working in hardware. 2x performance boost in some cases. 9 months ago
compileAndSend.sh 1026f4776c Cleaned up some files 1 year ago
simulate.sh 1026f4776c Cleaned up some files 1 year ago