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busProtocol_tb.v 1.6 KB

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  1. /*
  2. * Testbench
  3. * Simulates the bus protocol
  4. */
  5. `timescale 1 ns/1 ns
  6. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/testbench/busProtocol/cpu.v"
  7. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/testbench/busProtocol/mu.v"
  8. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/Memory/SRAM.v"
  9. module busProtocol_tb;
  10. reg clk;
  11. reg reset;
  12. reg clear;
  13. reg hold;
  14. // Bus
  15. wire [26:0] bus_addr;
  16. wire [31:0] bus_data;
  17. wire bus_we;
  18. wire bus_start;
  19. wire [31:0] bus_q;
  20. wire bus_done;
  21. MemoryUnit memoryunit(
  22. // Clocks
  23. .clk (clk),
  24. .reset (reset),
  25. // Bus
  26. .bus_addr (bus_addr),
  27. .bus_data (bus_data),
  28. .bus_we (bus_we),
  29. .bus_start (bus_start),
  30. .bus_q (bus_q),
  31. .bus_done (bus_done),
  32. .bus_ready (bus_ready)
  33. );
  34. //---------------CPU----------------
  35. CPU cpu(
  36. .clk (clk),
  37. .reset (reset),
  38. // bus
  39. .bus_addr (bus_addr),
  40. .bus_data (bus_data),
  41. .bus_we (bus_we),
  42. .bus_start (bus_start),
  43. .bus_q (bus_q),
  44. .bus_done (bus_done),
  45. .bus_ready (bus_ready),
  46. .clear (clear),
  47. .hold (hold)
  48. );
  49. initial
  50. begin
  51. //Dump everything for GTKwave
  52. $dumpfile("/home/bart/Documents/FPGA/FPGC6/Verilog/output/wave.vcd");
  53. $dumpvars;
  54. clk = 0;
  55. reset = 0;
  56. clear = 0;
  57. hold = 0;
  58. repeat(3)
  59. begin
  60. #10 clk = ~clk; //50MHz
  61. #10 clk = ~clk;
  62. end
  63. reset = 1;
  64. repeat(3)
  65. begin
  66. #10 clk = ~clk; //50MHz
  67. #10 clk = ~clk;
  68. end
  69. reset = 0;
  70. repeat(100)
  71. begin
  72. #10 clk = ~clk; //50MHz
  73. #10 clk = ~clk;
  74. end
  75. #1 $finish;
  76. end
  77. endmodule