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B32P_tb.v 2.4 KB

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  1. /*
  2. * Testbench
  3. * Simulates the CPU while using a simplified version of the rest of the system
  4. */
  5. // Set timescale
  6. `timescale 1 ns/1 ns
  7. // tld
  8. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/FPGC6Simplified.v"
  9. // other logic
  10. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/MultiStabilizer.v"
  11. // cpu
  12. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/CPU/CPU.v"
  13. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/CPU/ALU.v"
  14. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/CPU/ControlUnit.v"
  15. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/CPU/InstructionDecoder.v"
  16. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/CPU/Regbank.v"
  17. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/CPU/Stack.v"
  18. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/CPU/InstrMem.v"
  19. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/CPU/DataMem.v"
  20. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/CPU/Regr.v"
  21. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/CPU/IntController.v"
  22. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/CPU/L1Icache.v"
  23. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/CPU/L1Dcache.v"
  24. // memory
  25. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/Memory/SRAM.v"
  26. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/Memory/MemoryUnitSimplified.v"
  27. // Define testmodule
  28. module FPGC_tb;
  29. //Clock I/O
  30. reg clk;
  31. reg clk100;
  32. reg nreset;
  33. FPGC6 fpgc (
  34. .clk(clk),
  35. .clk100(clk100),
  36. .nreset(nreset)
  37. );
  38. initial
  39. begin
  40. //Dump everything for GTKwave
  41. $dumpfile("/home/bart/Documents/FPGA/FPGC6/Verilog/output/wave.vcd");
  42. $dumpvars;
  43. clk = 0;
  44. nreset = 1;
  45. repeat(3)
  46. begin
  47. #5 clk100 = ~clk100; clk = ~clk; //50MHz
  48. #5 clk100 = ~clk100; //100MHz
  49. #5 clk100 = ~clk100; clk = ~clk; //50MHz
  50. #5 clk100 = ~clk100; //100MHz
  51. end
  52. nreset = 0;
  53. repeat(3)
  54. begin
  55. #5 clk100 = ~clk100; clk = ~clk; //50MHz
  56. #5 clk100 = ~clk100; //100MHz
  57. #5 clk100 = ~clk100; clk = ~clk; //50MHz
  58. #5 clk100 = ~clk100; //100MHz
  59. end
  60. nreset = 1;
  61. repeat(1000)
  62. begin
  63. #5 clk100 = ~clk100; clk = ~clk; //50MHz
  64. #5 clk100 = ~clk100; //100MHz
  65. #5 clk100 = ~clk100; clk = ~clk; //50MHz
  66. #5 clk100 = ~clk100; //100MHz
  67. end
  68. #1 $finish;
  69. end
  70. endmodule