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SRAM.v 698 B

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  1. /*
  2. * SRAM implementation
  3. */
  4. module SRAM
  5. #(
  6. parameter WIDTH = 32,
  7. parameter WORDS = 4096,
  8. parameter ADDR_BITS = 12,
  9. parameter LIST = "/home/bart/Documents/FPGA/FPGC6/Verilog/memory/sram.list"
  10. )
  11. (
  12. input cpu_clk,
  13. input [WIDTH-1:0] cpu_d,
  14. input [ADDR_BITS-1:0] cpu_addr,
  15. input cpu_we,
  16. output reg [WIDTH-1:0] cpu_q
  17. );
  18. reg [WIDTH-1:0] ram [0:WORDS-1]; //basically the memory cells
  19. //cpu port
  20. always @(posedge cpu_clk)
  21. begin
  22. cpu_q <= ram[cpu_addr];
  23. if (cpu_we)
  24. begin
  25. cpu_q <= cpu_d;
  26. ram[cpu_addr] <= cpu_d;
  27. end
  28. end
  29. //initialize VRAM
  30. initial
  31. begin
  32. $readmemb(LIST, ram);
  33. end
  34. endmodule