FPGC6Simplified.v 1.2 KB

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  1. /*
  2. * Top level design of the FPGC6
  3. */
  4. module FPGC6(
  5. input clk, // 50MHz
  6. input clk100, // 100MHz
  7. input nreset,
  8. //Led for debugging
  9. output led
  10. );
  11. //--------------------Reset&Stabilizers-----------------------
  12. //Reset signals
  13. wire nreset_stable, reset;
  14. MultiStabilizer multistabilizer (
  15. .clk(clk),
  16. .u0(nreset),
  17. .s0(nreset_stable)
  18. );
  19. assign reset = ~nreset_stable;
  20. // Bus
  21. wire [26:0] bus_addr;
  22. wire [31:0] bus_data;
  23. wire bus_we;
  24. wire bus_start;
  25. wire [31:0] bus_q;
  26. wire bus_done;
  27. wire bus_ready;
  28. MemoryUnit memoryunit(
  29. // Clocks
  30. .clk (clk),
  31. .reset (reset),
  32. // Bus
  33. .bus_addr (bus_addr),
  34. .bus_data (bus_data),
  35. .bus_we (bus_we),
  36. .bus_start (bus_start),
  37. .bus_q (bus_q),
  38. .bus_done (bus_done),
  39. .bus_ready (bus_ready)
  40. );
  41. //---------------CPU----------------
  42. CPU cpu(
  43. .clk (clk),
  44. .clk100 (clk100),
  45. .reset (reset),
  46. // bus
  47. .bus_addr (bus_addr),
  48. .bus_data (bus_data),
  49. .bus_we (bus_we),
  50. .bus_start (bus_start),
  51. .bus_q (bus_q),
  52. .bus_done (bus_done),
  53. .bus_ready (bus_ready)
  54. );
  55. endmodule