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ALU.v
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3af9eecaa9
Added signed fixed point multiplication to ALU.
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пре 1 година |
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CPU.v
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9b3e3a5eb7
Initial progress with faster design.
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пре 2 месеци |
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ControlUnit.v
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7e81e7fa17
Added files missing from last commit (L1I cache).
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пре 1 година |
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DataMem.v
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9b3e3a5eb7
Initial progress with faster design.
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пре 2 месеци |
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InstrMem.v
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9b3e3a5eb7
Initial progress with faster design.
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пре 2 месеци |
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InstructionDecoder.v
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9f74a9565f
Fixed more MU I/O bugs. Updated everything from BCC except the ASM to work on new CPU. Added back flasher programs. Fixed LOAD/HI bug by using unsigned const16 instead. Updated assembler including hotfix for FPGC jumping to addr3 after UART bootloader is done. FPGC6 now basically fully works again!
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пре 2 година |
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IntController.v
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207413dd90
Assembler only needs Int: function, fixed position of program lenght. Ported ROM and UART bootloader over from FPGC5. Updated documentation on interrupts. Added resets. Fixed bug in MU. Increased stack size. Tested everything in hardware. Probably some other fixes and things I forgot.
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пре 2 година |
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Regbank.v
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28bcde6466
New SDRAM controller that uses both SDRAM chips. Now separate bus from MU for better performance, as controller runs at 100MHz. Also updated some debug code as debugging was needed. Tested working in hardware. 2x performance boost in some cases.
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пре 1 година |
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Regr.v
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302c69937e
Basic CPU design now done with afaik working hazard detection, forwarding and stalls. Tested in hardware on a EP4CE6 using two SSDisplays and dip switches to view the register content (and see if it matches the simulation). No interrupts yet as this can probably be done at a later stage.
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пре 2 година |
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Stack.v
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207413dd90
Assembler only needs Int: function, fixed position of program lenght. Ported ROM and UART bootloader over from FPGC5. Updated documentation on interrupts. Added resets. Fixed bug in MU. Increased stack size. Tested everything in hardware. Probably some other fixes and things I forgot.
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пре 2 година |
bartpleiter
9b3e3a5eb7
Initial progress with faster design.