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bart f78729ea77 Fixed L2 cache state machine issue which was only present in the previous commit. před 1 rokem
Assembler 7e81e7fa17 Added files missing from last commit (L1I cache). před 1 rokem
BCC 52f2819774 Removed leftover ccache instructions from debugging instability problems. Commented out required ccache instructions for when L1I cache returns in the future. před 1 rokem
Documentation 9a285550c0 Updated documentation a bit, added newlines to BENCH, removed wrong comments from L2cache.v před 1 rokem
Graphics c4599a63cc New documentation structure. Updated some documentation. Added relevant graphics scripts and files from FPGC5 repo. před 2 roky
Programmer 52f2819774 Removed leftover ccache instructions from debugging instability problems. Commented out required ccache instructions for when L1I cache returns in the future. před 1 rokem
Quartus f78729ea77 Fixed L2 cache state machine issue which was only present in the previous commit. před 1 rokem
SublimeText3 1026f4776c Cleaned up some files před 2 roky
Verilog f78729ea77 Fixed L2 cache state machine issue which was only present in the previous commit. před 1 rokem
.gitattributes b9bc26129d Added gitattributes to ignore the huge UARTbootloader.asm file. Deleted old quartus test project. před 2 roky
.gitignore a76905443f Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work. před 2 roky
LICENSE.txt 9ec3298860 Updated README and added licence so repo can go public now před 2 roky
README.md 3d9b4194f7 Added initial documentation před 2 roky

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