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Assembler
bart 7e81e7fa17 Added files missing from last commit (L1I cache). 1 tahun lalu
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Bootloaders 7e81e7fa17 Added files missing from last commit (L1I cache). 1 tahun lalu
SimTests 28bcde6466 New SDRAM controller that uses both SDRAM chips. Now separate bus from MU for better performance, as controller runs at 100MHz. Also updated some debug code as debugging was needed. Tested working in hardware. 2x performance boost in some cases. 1 tahun lalu
Assembler.py 7e81e7fa17 Added files missing from last commit (L1I cache). 1 tahun lalu
CompileInstruction.py 7e81e7fa17 Added files missing from last commit (L1I cache). 1 tahun lalu
buildToVerilog.sh 28bcde6466 New SDRAM controller that uses both SDRAM chips. Now separate bus from MU for better performance, as controller runs at 100MHz. Also updated some debug code as debugging was needed. Tested working in hardware. 2x performance boost in some cases. 1 tahun lalu
compileAndSend.sh 1026f4776c Cleaned up some files 2 tahun lalu
simulate.sh 1026f4776c Cleaned up some files 2 tahun lalu