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B32P_tb.v
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b6831c4209
Added L2 cache (no L1 for now) between CPU and SDRAM controller. No noticable performance difference, can likely be optimized further to reduce cache hit latency.
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1 anno fa |
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FPGC_tb.v
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f3f3a43044
Added fixed-point signed divider to MU. Integrated into FPCALC.
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1 anno fa |
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FSX_tb.v
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6e3cd7cd9c
PixelEngine now works in hardware with both HDMI and NTSC. Added pxtest and mandelbrot test programs.
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2 anni fa |
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SDRAM_tb.v
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28bcde6466
New SDRAM controller that uses both SDRAM chips. Now separate bus from MU for better performance, as controller runs at 100MHz. Also updated some debug code as debugging was needed. Tested working in hardware. 2x performance boost in some cases.
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1 anno fa |
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divider_tb.v
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f3f3a43044
Added fixed-point signed divider to MU. Integrated into FPCALC.
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1 anno fa |
bart
f3f3a43044
Added fixed-point signed divider to MU. Integrated into FPCALC.