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clkMux
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e1bb01a621
Cleaned and renamed Quartus project.
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1 年間 前 |
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clock_pll_v
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a76905443f
Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work.
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2 年 前 |
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clock_pll_v_sim
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e1bb01a621
Cleaned and renamed Quartus project.
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1 年間 前 |
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memory
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7e81e7fa17
Added files missing from last commit (L1I cache).
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1 年間 前 |
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modules
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da2bff2ea2
Removed/disabled NTSC from design, as the tiny HDMI monitor is practically always used. Also greatly increased L2 cache size, although no performance benefits for the relatively small programs I currently use for benchmarking.
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1 年間 前 |
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output_files
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da2bff2ea2
Removed/disabled NTSC from design, as the tiny HDMI monitor is practically always used. Also greatly increased L2 cache size, although no performance benefits for the relatively small programs I currently use for benchmarking.
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1 年間 前 |
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FPGC.qpf
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e1bb01a621
Cleaned and renamed Quartus project.
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1 年間 前 |
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FPGC.qsf
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da2bff2ea2
Removed/disabled NTSC from design, as the tiny HDMI monitor is practically always used. Also greatly increased L2 cache size, although no performance benefits for the relatively small programs I currently use for benchmarking.
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1 年間 前 |
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FPGC.qws
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da2bff2ea2
Removed/disabled NTSC from design, as the tiny HDMI monitor is practically always used. Also greatly increased L2 cache size, although no performance benefits for the relatively small programs I currently use for benchmarking.
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1 年間 前 |
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FPGC.sdc
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e1bb01a621
Cleaned and renamed Quartus project.
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1 年間 前 |
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NTSC_pll.ppf
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da2bff2ea2
Removed/disabled NTSC from design, as the tiny HDMI monitor is practically always used. Also greatly increased L2 cache size, although no performance benefits for the relatively small programs I currently use for benchmarking.
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1 年間 前 |
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NTSC_pll.qip
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b74702c915
Created full FPGC6 verilog simulation, added Quartus code from FPGC5 with CPU from FPGC6. Works in hardware, but has combination loop somewhere at the arbiter and the registerbank and stack are not using block ram
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2 年 前 |
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NTSC_pll.v
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da2bff2ea2
Removed/disabled NTSC from design, as the tiny HDMI monitor is practically always used. Also greatly increased L2 cache size, although no performance benefits for the relatively small programs I currently use for benchmarking.
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1 年間 前 |
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NTSC_pll_bb.v
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da2bff2ea2
Removed/disabled NTSC from design, as the tiny HDMI monitor is practically always used. Also greatly increased L2 cache size, although no performance benefits for the relatively small programs I currently use for benchmarking.
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1 年間 前 |
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clkMux.qsys
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a76905443f
Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work.
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2 年 前 |
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clkMux.sopcinfo
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a76905443f
Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work.
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2 年 前 |
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clock_pll.ppf
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da2bff2ea2
Removed/disabled NTSC from design, as the tiny HDMI monitor is practically always used. Also greatly increased L2 cache size, although no performance benefits for the relatively small programs I currently use for benchmarking.
|
1 年間 前 |
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clock_pll.qip
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b74702c915
Created full FPGC6 verilog simulation, added Quartus code from FPGC5 with CPU from FPGC6. Works in hardware, but has combination loop somewhere at the arbiter and the registerbank and stack are not using block ram
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2 年 前 |
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clock_pll.v
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da2bff2ea2
Removed/disabled NTSC from design, as the tiny HDMI monitor is practically always used. Also greatly increased L2 cache size, although no performance benefits for the relatively small programs I currently use for benchmarking.
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1 年間 前 |
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clock_pll_bb.v
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da2bff2ea2
Removed/disabled NTSC from design, as the tiny HDMI monitor is practically always used. Also greatly increased L2 cache size, although no performance benefits for the relatively small programs I currently use for benchmarking.
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1 年間 前 |
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clock_pll_v.cmp
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a76905443f
Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work.
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2 年 前 |
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clock_pll_v.qip
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a76905443f
Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work.
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2 年 前 |
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clock_pll_v.sip
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a76905443f
Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work.
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2 年 前 |
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clock_pll_v.spd
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a76905443f
Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work.
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2 年 前 |
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clock_pll_v.v
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a76905443f
Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work.
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2 年 前 |
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ddr.ppf
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a76905443f
Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work.
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2 年 前 |
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ddr.qip
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a76905443f
Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work.
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2 年 前 |
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ddr.v
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a76905443f
Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work.
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2 年 前 |
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ddr_bb.v
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a76905443f
Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work.
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2 年 前 |
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output_file.cof
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e1bb01a621
Cleaned and renamed Quartus project.
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1 年間 前 |
bart
da2bff2ea2
Removed/disabled NTSC from design, as the tiny HDMI monitor is practically always used. Also greatly increased L2 cache size, although no performance benefits for the relatively small programs I currently use for benchmarking.