1
0

divider.gtkw 882 B

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  1. [*]
  2. [*] GTKWave Analyzer v3.3.107 (w)1999-2020 BSI
  3. [*] Fri Sep 15 17:19:10 2023
  4. [*]
  5. [dumpfile] "/home/bart/Documents/FPGA/FPGC6/Verilog/output/wave.vcd"
  6. [dumpfile_mtime] "Fri Sep 15 17:05:26 2023"
  7. [dumpfile_size] 7596
  8. [savefile] "/home/bart/Documents/FPGA/FPGC6/Verilog/output/divider.gtkw"
  9. [timestart] 0
  10. [size] 1920 1054
  11. [pos] -1 -1
  12. *-8.000000 567 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
  13. [treeopen] divider_tb.
  14. [sst_width] 227
  15. [signals_width] 169
  16. [sst_expanded] 1
  17. [sst_vpaned_height] 293
  18. @28
  19. divider_tb.clk
  20. divider_tb.reset
  21. @200
  22. -
  23. @24
  24. divider_tb.a[31:0]
  25. divider_tb.b[31:0]
  26. divider_tb.val[31:0]
  27. divider_tb.val_int[15:0]
  28. @200
  29. -
  30. @22
  31. divider_tb.divider.a[31:0]
  32. @23
  33. divider_tb.divider.b[31:0]
  34. @28
  35. divider_tb.write_a
  36. divider_tb.start
  37. divider_tb.busy
  38. divider_tb.done
  39. divider_tb.valid
  40. divider_tb.dbz
  41. divider_tb.ovf
  42. [pattern_trace] 1
  43. [pattern_trace] 0