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MultiStabilizer.v 1.7 KB

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  1. /*
  2. * Stabilizes multiple input signals (up to 16) to the clock domain,
  3. * by using a double register synchronizer chain.
  4. */
  5. module MultiStabilizer (
  6. input clk,
  7. // unstable input signals
  8. input u0, u1, u2, u3, u4, u5, u6, u7, u8, u9, u10, u11, u12, u13, u14, u15,
  9. // stable output signals
  10. output s0, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15
  11. );
  12. // chains
  13. reg [1:0] c0, c1, c2, c3, c4, c5, c6, c7, c8, c9, c10, c11, c12, c13, c14, c15;
  14. always @(posedge clk)
  15. begin
  16. c0[0] <= u0;
  17. c0[1] <= c0[0];
  18. c1[0] <= u1;
  19. c1[1] <= c1[0];
  20. c2[0] <= u2;
  21. c2[1] <= c2[0];
  22. c3[0] <= u3;
  23. c3[1] <= c3[0];
  24. c4[0] <= u4;
  25. c4[1] <= c4[0];
  26. c5[0] <= u5;
  27. c5[1] <= c5[0];
  28. c6[0] <= u6;
  29. c6[1] <= c6[0];
  30. c7[0] <= u7;
  31. c7[1] <= c7[0];
  32. c8[0] <= u8;
  33. c8[1] <= c8[0];
  34. c9[0] <= u9;
  35. c9[1] <= c9[0];
  36. c10[0] <= u10;
  37. c10[1] <= c10[0];
  38. c11[0] <= u11;
  39. c11[1] <= c11[0];
  40. c12[0] <= u12;
  41. c12[1] <= c12[0];
  42. c13[0] <= u13;
  43. c13[1] <= c13[0];
  44. c14[0] <= u14;
  45. c14[1] <= c14[0];
  46. c15[0] <= u15;
  47. c15[1] <= c15[0];
  48. end
  49. assign s0 = c0[1];
  50. assign s1 = c1[1];
  51. assign s2 = c2[1];
  52. assign s3 = c3[1];
  53. assign s4 = c4[1];
  54. assign s5 = c5[1];
  55. assign s6 = c6[1];
  56. assign s7 = c7[1];
  57. assign s8 = c8[1];
  58. assign s9 = c9[1];
  59. assign s10 = c10[1];
  60. assign s11 = c11[1];
  61. assign s12 = c12[1];
  62. assign s13 = c13[1];
  63. assign s14 = c14[1];
  64. assign s15 = c15[1];
  65. endmodule