OStimer.v 2.2 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990
  1. // One shot timer that counts in milliseconds
  2. // Uses a delay of sysClkMHz-1 cycles per timerValue
  3. module OStimer(
  4. input clk,
  5. input reset,
  6. input [31:0] timerValue,
  7. input trigger,
  8. input setValue,
  9. output reg interrupt = 1'b0
  10. );
  11. // States
  12. localparam s_idle = 0;
  13. localparam s_start = 1;
  14. localparam s_done = 2;
  15. parameter delay = 49999; // Clock cycles delay per timerValue, could eventually become programmable, should then default to 1ms
  16. reg [31:0] counterValue = 32'd0; // 32 bits for timerValue
  17. reg [31:0] delayCounter = 32'd0; // counter for timer delay
  18. reg [1:0] state = s_idle; // state of timer
  19. always @(posedge clk)
  20. begin
  21. if (reset)
  22. begin
  23. counterValue <= 32'd0;
  24. delayCounter <= 32'd0;
  25. state <= s_idle;
  26. interrupt <= 1'd0;
  27. end
  28. else
  29. begin
  30. if (setValue)
  31. begin
  32. counterValue <= timerValue;
  33. end
  34. else
  35. begin
  36. case (state)
  37. s_idle:
  38. begin
  39. if (trigger)
  40. begin
  41. state <= s_start;
  42. delayCounter <= delay;
  43. end
  44. end
  45. s_start:
  46. begin
  47. if (counterValue == 32'd0)
  48. begin
  49. state <= s_done;
  50. interrupt <= 1'b1;
  51. end
  52. else
  53. begin
  54. if (delayCounter == 32'd0)
  55. begin
  56. counterValue <= counterValue - 1'b1;
  57. delayCounter <= delay;
  58. end
  59. else
  60. begin
  61. delayCounter <= delayCounter - 1'b1;
  62. end
  63. end
  64. end
  65. s_done:
  66. begin
  67. interrupt <= 1'b0;
  68. state <= s_idle;
  69. end
  70. endcase
  71. end
  72. end
  73. end
  74. endmodule