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DataMem.v 1.1 KB

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  1. /*
  2. * Data Memory
  3. */
  4. module DataMem(
  5. input wire clk, reset,
  6. input wire [31:0] addr,
  7. input wire we,
  8. input wire re,
  9. input wire [31:0] data,
  10. output wire [31:0] q,
  11. output busy,
  12. // bus
  13. output [31:0] bus_addr,
  14. output [31:0] bus_data,
  15. output bus_we,
  16. output bus_start,
  17. input [31:0] bus_q,
  18. input bus_done,
  19. input wire clear, hold
  20. );
  21. reg [31:0] qreg = 32'd0;
  22. assign bus_addr = addr;
  23. assign bus_data = data;
  24. assign bus_we = we;
  25. assign bus_start = !bus_done && (we || re);
  26. assign busy = bus_start;
  27. assign q = (bus_done) ? bus_q : qreg;
  28. always @(posedge clk)
  29. begin
  30. // skip clear, because currently not needed
  31. /*if (clear)
  32. begin
  33. q <= 32'd0;
  34. end
  35. else */
  36. // skip hold, because currently not needed
  37. /*
  38. if (hold)
  39. begin
  40. q <= q;
  41. end
  42. else */
  43. if (reset)
  44. begin
  45. qreg <= 32'd0;
  46. end
  47. else
  48. begin
  49. if (bus_done)
  50. begin
  51. qreg <= bus_q;
  52. end
  53. end
  54. end
  55. endmodule