bart f78729ea77 Fixed L2 cache state machine issue which was only present in the previous commit. 1 year ago
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bin2txt.sh 9662964536 Added back scripts for converting to spi.txt. Tested code to run from SPI flash, fixed cycle delay for SPI flash in output latch in MU which caused the bus_q to arrive a cycle later than bus_done. 2 years ago
code.bin f78729ea77 Fixed L2 cache state machine issue which was only present in the previous commit. 1 year ago
rom.list 7e81e7fa17 Added files missing from last commit (L1I cache). 1 year ago
spi.txt f78729ea77 Fixed L2 cache state machine issue which was only present in the previous commit. 1 year ago
vram32.list 916054063a Added MU from FPGC5, created arbiter to regulate access to the CPU memory bus from both Instruction and Data memory, created fast testbench for arbiter, can now start adding arbiter and MU to CPU design 2 years ago
vram8.list b74702c915 Created full FPGC6 verilog simulation, added Quartus code from FPGC5 with CPU from FPGC6. Works in hardware, but has combination loop somewhere at the arbiter and the registerbank and stack are not using block ram 2 years ago
vramPX.list 7b14d2d273 Improved Pixel Engine. 1 year ago
vramSPR.list b74702c915 Created full FPGC6 verilog simulation, added Quartus code from FPGC5 with CPU from FPGC6. Works in hardware, but has combination loop somewhere at the arbiter and the registerbank and stack are not using block ram 2 years ago