L2cache.v 7.8 KB

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  1. /*
  2. * L2 Cache
  3. * Sits between CPU and SDRAM controller
  4. * Made to run at 100MHz
  5. */
  6. module L2cache(
  7. // clock/reset inputs
  8. input clk,
  9. input reset,
  10. // CPU bus
  11. input [23:0] l2_addr,
  12. input [31:0] l2_data,
  13. input l2_we,
  14. input l2_start,
  15. output [31:0] l2_q,
  16. output l2_done,
  17. // SDRAM controller bus
  18. output [23:0] sdc_addr,
  19. output [31:0] sdc_data,
  20. output sdc_we,
  21. output sdc_start,
  22. input [31:0] sdc_q,
  23. input sdc_done
  24. );
  25. wire cache_reset;
  26. assign cache_reset = 1'b0;
  27. parameter cache_size = 1024; // cache size in words. 8129*4bytes = 32KiB
  28. parameter index_size = 10; // index size: log2(cache_size)
  29. parameter tag_size = 14; // mem_add_bits-index_size = 24-13 = 11
  30. parameter cache_line_size = tag_size+32+1; // tag + word + valid bit
  31. reg [cache_line_size-1:0] cache [0:cache_size-1]; // cache memory
  32. integer i;
  33. // init cache to all zeros
  34. initial
  35. begin
  36. for (i = 0; i < cache_size; i = i + 1)
  37. begin
  38. cache[i] = 47'd0;
  39. end
  40. end
  41. reg [index_size-1:0] cache_addr = 10'd0;
  42. reg [cache_line_size-1:0] cache_d = 47'd0;
  43. reg cache_we = 1'b0;
  44. reg [cache_line_size-1:0] cache_q = 47'd0;
  45. always @(posedge clk)
  46. begin
  47. cache_q <= cache[cache_addr];
  48. if (cache_we)
  49. begin
  50. cache[cache_addr] <= cache_d;
  51. $display("%d: wrote to l2 cache", $time);
  52. end
  53. end
  54. reg [31:0] l2_q_reg = 32'd0;
  55. reg l2_done_reg = 1'b0;
  56. reg [23:0] sdc_addr_reg = 24'd0;
  57. reg [31:0] sdc_data_reg = 32'd0;
  58. reg sdc_we_reg = 1'b0;
  59. reg sdc_start_reg = 1'b0;
  60. reg start_prev = 1'b0;
  61. // state machine
  62. reg [2:0] state = 3'd0; // 0-7 states limit
  63. parameter state_init = 3'd0;
  64. parameter state_idle = 3'd1;
  65. parameter state_writing = 3'd2;
  66. parameter state_check_cache = 3'd3;
  67. parameter state_miss_read_ram = 3'd4;
  68. parameter state_delay_cache = 3'd5;
  69. parameter state_done_high = 3'd6;
  70. parameter state_clear_cache = 3'd7;
  71. reg [31:0] addr_prev = 32'd0;
  72. reg [15:0] clear_cache_counter = 16'd0; // 64k max
  73. reg start_registered = 1'b0;
  74. always @(posedge clk)
  75. begin
  76. if (reset)
  77. begin
  78. l2_q_reg <= 32'd0;
  79. l2_done_reg <= 1'b0;
  80. sdc_addr_reg <= 24'd0;
  81. sdc_data_reg <= 32'd0;
  82. sdc_we_reg <= 1'b0;
  83. sdc_start_reg <= 1'b0;
  84. addr_prev <= 32'd0;
  85. // Make sure the next cycle a new request can be detected!
  86. start_prev <= 1'b0;
  87. state <= state_clear_cache;
  88. clear_cache_counter <= 16'd0;
  89. start_registered <= 1'b0;
  90. end
  91. else
  92. begin
  93. addr_prev <= l2_addr;
  94. start_prev <= l2_start;
  95. l2_done_reg <= 1'b0;
  96. cache_we <= 1'b0;
  97. // NOTE: make sure to use latched l2_addr from rising start to make sure all addresses are correct!
  98. // as l2_addr can change during a clear/skipresult (e.g. when jump or other pipeline flush)
  99. case(state)
  100. state_init:
  101. begin
  102. state <= state_clear_cache;
  103. end
  104. state_clear_cache:
  105. begin
  106. if (l2_addr < 27'h800000 && ( (l2_start && !start_prev) || addr_prev >= 27'h800000 && l2_start) )
  107. begin
  108. start_registered <= 1'b1;
  109. end
  110. if (clear_cache_counter == cache_size)
  111. begin
  112. clear_cache_counter <= 16'd0;
  113. state <= state_idle;
  114. end
  115. else
  116. begin
  117. clear_cache_counter <= clear_cache_counter + 1'b1;
  118. cache_we <= 1'b1;
  119. cache_d <= 47'd0;
  120. cache_addr <= clear_cache_counter;
  121. end
  122. end
  123. state_idle:
  124. begin
  125. if (l2_addr < 27'h800000)
  126. begin
  127. if ( ( (l2_start && !start_prev) || addr_prev >= 27'h800000 && l2_start) || start_registered)
  128. begin
  129. start_registered <= 1'b0;
  130. if (l2_we)
  131. begin
  132. // update cache and write SDRAM
  133. state <= state_writing;
  134. sdc_addr_reg <= l2_addr;
  135. sdc_we_reg <= 1'b1;
  136. sdc_start_reg <= 1'b1;
  137. sdc_data_reg <= l2_data;
  138. cache_d <= {1'b1, l2_addr[23:index_size], l2_data}; // tag + data
  139. cache_addr <= l2_addr[index_size-1:0];
  140. end
  141. else
  142. begin
  143. // wait a cycle for cache to be read
  144. cache_addr <= l2_addr[index_size-1:0];
  145. state <= state_delay_cache;
  146. // just in case we have a cache miss in the next cycle, prepare address on sdram controller bus
  147. sdc_addr_reg <= l2_addr;
  148. sdc_we_reg <= 1'b0;
  149. end
  150. end
  151. end
  152. end
  153. state_delay_cache:
  154. begin
  155. state <= state_check_cache;
  156. end
  157. state_writing:
  158. begin
  159. if (sdc_done)
  160. begin
  161. state <= state_done_high;
  162. sdc_addr_reg <= 24'd0;
  163. sdc_we_reg <= 1'b0;
  164. sdc_start_reg <= 1'b0;
  165. sdc_data_reg <= 32'd0;
  166. cache_we <= 1'b1;
  167. l2_done_reg <= 1'b1;
  168. end
  169. end
  170. state_check_cache:
  171. begin
  172. // check cache. if hit, return cached item
  173. if (cache_q[46] && sdc_addr_reg[23:index_size] == cache_q[45:32]) // valid and tag check
  174. begin
  175. state <= state_done_high;
  176. l2_done_reg <= 1'b1;
  177. l2_q_reg <= cache_q[31:0];
  178. end
  179. // if miss, read from ram, place in cache, return cached item
  180. else
  181. begin
  182. state <= state_miss_read_ram;
  183. sdc_start_reg <= 1'b1;
  184. end
  185. end
  186. state_miss_read_ram:
  187. begin
  188. if (sdc_done)
  189. begin
  190. state <= state_done_high;
  191. // we received item from ram, now write to cache and return
  192. sdc_addr_reg <= 24'd0;
  193. sdc_start_reg <= 1'b0;
  194. cache_we <= 1'b1;
  195. cache_d <= {1'b1, sdc_addr_reg[23:index_size], sdc_q}; // tag + data
  196. l2_done_reg <= 1'b1;
  197. l2_q_reg <= sdc_q;
  198. end
  199. end
  200. state_done_high:
  201. begin
  202. // keep done high for one cycle as we run on double clock speed from CPU
  203. l2_done_reg <= 1'b1;
  204. state <= state_idle;
  205. end
  206. endcase
  207. end
  208. end
  209. // passthrough when above SDRAM memory range
  210. assign sdc_addr = (l2_addr < 27'h800000) ? sdc_addr_reg : l2_addr;
  211. assign sdc_data = (l2_addr < 27'h800000) ? sdc_data_reg : l2_data;
  212. assign sdc_we = (l2_addr < 27'h800000) ? sdc_we_reg : l2_we;
  213. assign sdc_start = (l2_addr < 27'h800000) ? sdc_start_reg : l2_start;
  214. assign l2_q = (l2_addr < 27'h800000) ? l2_q_reg : sdc_q;
  215. assign l2_done = (l2_addr < 27'h800000) ? l2_done_reg : sdc_done;
  216. endmodule