Regr.v 509 B

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  1. /*
  2. * Register that can be cleared or held
  3. * Useful for passing data between CPU stages
  4. */
  5. module Regr(
  6. input clk,
  7. input clear,
  8. input hold,
  9. input wire [N-1:0] in,
  10. output reg [N-1:0] out
  11. );
  12. parameter N = 1;
  13. always @(posedge clk)
  14. begin
  15. if (clear)
  16. begin
  17. out <= {N{1'b0}};
  18. end
  19. else if (hold)
  20. begin
  21. out <= out;
  22. end
  23. else
  24. begin
  25. out <= in;
  26. end
  27. end
  28. initial
  29. begin
  30. out <= {N{1'b0}};
  31. end
  32. endmodule