ControlUnit.v 2.7 KB

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  1. /*
  2. * Control Unit
  3. */
  4. module ControlUnit(
  5. input [3:0] instrOP,
  6. input he,
  7. output reg alu_use_const,
  8. output reg push, pop,
  9. output reg dreg_we,
  10. output reg mem_write, mem_read,
  11. output reg jumpc, jumpr, branch, halt, reti,
  12. output reg getIntID, getPC, clearCache
  13. );
  14. // Instruction Opcodes
  15. localparam
  16. OP_HALT = 4'b1111,
  17. OP_READ = 4'b1110,
  18. OP_WRITE = 4'b1101,
  19. OP_INTID = 4'b1100,
  20. OP_PUSH = 4'b1011,
  21. OP_POP = 4'b1010,
  22. OP_JUMP = 4'b1001,
  23. OP_JUMPR = 4'b1000,
  24. OP_CCACHE = 4'b0111,
  25. OP_BRANCH = 4'b0110,
  26. OP_SAVPC = 4'b0101,
  27. OP_RETI = 4'b0100,
  28. OP_UNDEF2 = 4'b0011, // undefined
  29. OP_UNDEF3 = 4'b0010, // undefined
  30. OP_ARITHC = 4'b0001,
  31. OP_ARITH = 4'b0000;
  32. always @(*) begin
  33. // default
  34. alu_use_const <= 1'b0;
  35. push <= 1'b0;
  36. pop <= 1'b0;
  37. dreg_we <= 1'b0;
  38. mem_write <= 1'b0;
  39. mem_read <= 1'b0;
  40. jumpc <= 1'b0;
  41. jumpr <= 1'b0;
  42. getIntID <= 1'b0;
  43. getPC <= 1'b0;
  44. branch <= 1'b0;
  45. halt <= 1'b0;
  46. reti <= 1'b0;
  47. clearCache <= 1'b0;
  48. case (instrOP)
  49. OP_HALT:
  50. begin
  51. halt <= 1'b1;
  52. end
  53. OP_READ:
  54. begin
  55. mem_read <= 1'b1;
  56. dreg_we <= 1'b1;
  57. end
  58. OP_WRITE:
  59. begin
  60. mem_write <= 1'b1;
  61. end
  62. OP_INTID: // write interrupt ID to dreg
  63. begin
  64. getIntID <= 1'b1;
  65. dreg_we <= 1'b1;
  66. end
  67. OP_PUSH: // push reg to stack
  68. begin
  69. push <= 1'b1;
  70. end
  71. OP_POP: // pop stack tot reg
  72. begin
  73. dreg_we <= 1'b1;
  74. pop <= 1'b1;
  75. end
  76. OP_JUMP:
  77. begin
  78. jumpc <= 1'b1;
  79. end
  80. OP_JUMPR:
  81. begin
  82. jumpr <= 1'b1;
  83. end
  84. OP_BRANCH:
  85. begin
  86. branch <= 1'b1;
  87. end
  88. OP_SAVPC: // write PC to dreg
  89. begin
  90. getPC <= 1'b1;
  91. dreg_we <= 1'b1;
  92. end
  93. OP_RETI:
  94. begin
  95. reti <= 1'b1;
  96. end
  97. OP_CCACHE:
  98. begin
  99. clearCache <= 1'b1;
  100. end
  101. OP_ARITH:
  102. begin
  103. dreg_we <= 1'b1;
  104. end
  105. OP_ARITHC:
  106. begin
  107. alu_use_const <= 1'b1;
  108. dreg_we <= 1'b1;
  109. end
  110. endcase
  111. end
  112. endmodule