vcs_setup.sh 6.2 KB

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  1. # (C) 2001-2023 Altera Corporation. All rights reserved.
  2. # Your use of Altera Corporation's design tools, logic functions and
  3. # other software and tools, and its AMPP partner logic functions, and
  4. # any output files any of the foregoing (including device programming
  5. # or simulation files), and any associated documentation or information
  6. # are expressly subject to the terms and conditions of the Altera
  7. # Program License Subscription Agreement, Altera MegaCore Function
  8. # License Agreement, or other applicable license agreement, including,
  9. # without limitation, that your use is for the sole purpose of
  10. # programming logic devices manufactured by Altera and sold by Altera
  11. # or its authorized distributors. Please refer to the applicable
  12. # agreement for further details.
  13. # ACDS 21.1 850 linux 2023.09.03.15:07:27
  14. # ----------------------------------------
  15. # vcs - auto-generated simulation script
  16. # ----------------------------------------
  17. # This script provides commands to simulate the following IP detected in
  18. # your Quartus project:
  19. # mainpll
  20. #
  21. # Altera recommends that you source this Quartus-generated IP simulation
  22. # script from your own customized top-level script, and avoid editing this
  23. # generated script.
  24. #
  25. # To write a top-level shell script that compiles Altera simulation libraries
  26. # and the Quartus-generated IP in your project, along with your design and
  27. # testbench files, follow the guidelines below.
  28. #
  29. # 1) Copy the shell script text from the TOP-LEVEL TEMPLATE section
  30. # below into a new file, e.g. named "vcs_sim.sh".
  31. #
  32. # 2) Copy the text from the DESIGN FILE LIST & OPTIONS TEMPLATE section into
  33. # a separate file, e.g. named "filelist.f".
  34. #
  35. # ----------------------------------------
  36. # # TOP-LEVEL TEMPLATE - BEGIN
  37. # #
  38. # # TOP_LEVEL_NAME is used in the Quartus-generated IP simulation script to
  39. # # set the top-level simulation or testbench module/entity name.
  40. # #
  41. # # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
  42. # # construct paths to the files required to simulate the IP in your Quartus
  43. # # project. By default, the IP script assumes that you are launching the
  44. # # simulator from the IP script location. If launching from another
  45. # # location, set QSYS_SIMDIR to the output directory you specified when you
  46. # # generated the IP script, relative to the directory from which you launch
  47. # # the simulator.
  48. # #
  49. # # Source the Quartus-generated IP simulation script and do the following:
  50. # # - Compile the Quartus EDA simulation library and IP simulation files.
  51. # # - Specify TOP_LEVEL_NAME and QSYS_SIMDIR.
  52. # # - Compile the design and top-level simulation module/entity using
  53. # # information specified in "filelist.f".
  54. # # - Override the default USER_DEFINED_SIM_OPTIONS. For example, to run
  55. # # until $finish(), set to an empty string: USER_DEFINED_SIM_OPTIONS="".
  56. # # - Run the simulation.
  57. # #
  58. # source <script generation output directory>/synopsys/vcs/vcs_setup.sh \
  59. # TOP_LEVEL_NAME=<simulation top> \
  60. # QSYS_SIMDIR=<script generation output directory> \
  61. # USER_DEFINED_ELAB_OPTIONS="\"-f filelist.f\"" \
  62. # USER_DEFINED_SIM_OPTIONS=<simulation options for your design>
  63. # #
  64. # # TOP-LEVEL TEMPLATE - END
  65. # ----------------------------------------
  66. #
  67. # ----------------------------------------
  68. # # DESIGN FILE LIST & OPTIONS TEMPLATE - BEGIN
  69. # #
  70. # # Compile all design files and testbench files, including the top level.
  71. # # (These are all the files required for simulation other than the files
  72. # # compiled by the Quartus-generated IP simulation script)
  73. # #
  74. # +systemverilogext+.sv
  75. # <design and testbench files, compile-time options, elaboration options>
  76. # #
  77. # # DESIGN FILE LIST & OPTIONS TEMPLATE - END
  78. # ----------------------------------------
  79. #
  80. # IP SIMULATION SCRIPT
  81. # ----------------------------------------
  82. # If mainpll is one of several IP cores in your
  83. # Quartus project, you can generate a simulation script
  84. # suitable for inclusion in your top-level simulation
  85. # script by running the following command line:
  86. #
  87. # ip-setup-simulation --quartus-project=<quartus project>
  88. #
  89. # ip-setup-simulation will discover the Altera IP
  90. # within the Quartus project, and generate a unified
  91. # script which supports all the Altera IP within the design.
  92. # ----------------------------------------
  93. # ACDS 21.1 850 linux 2023.09.03.15:07:27
  94. # ----------------------------------------
  95. # initialize variables
  96. TOP_LEVEL_NAME="mainpll"
  97. QSYS_SIMDIR="./../../"
  98. QUARTUS_INSTALL_DIR="/home/bart/intelFPGA_lite/21.1/quartus/"
  99. SKIP_FILE_COPY=0
  100. SKIP_SIM=0
  101. USER_DEFINED_ELAB_OPTIONS=""
  102. USER_DEFINED_SIM_OPTIONS="+vcs+finish+100"
  103. # ----------------------------------------
  104. # overwrite variables - DO NOT MODIFY!
  105. # This block evaluates each command line argument, typically used for
  106. # overwriting variables. An example usage:
  107. # sh <simulator>_setup.sh SKIP_SIM=1
  108. for expression in "$@"; do
  109. eval $expression
  110. if [ $? -ne 0 ]; then
  111. echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2
  112. exit $?
  113. fi
  114. done
  115. # ----------------------------------------
  116. # initialize simulation properties - DO NOT MODIFY!
  117. ELAB_OPTIONS=""
  118. SIM_OPTIONS=""
  119. if [[ `vcs -platform` != *"amd64"* ]]; then
  120. :
  121. else
  122. :
  123. fi
  124. # ----------------------------------------
  125. # copy RAM/ROM files to simulation directory
  126. vcs -lca -timescale=1ps/1ps -sverilog +verilog2001ext+.v -ntb_opts dtm $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS \
  127. -v $QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.v \
  128. -v $QUARTUS_INSTALL_DIR/eda/sim_lib/220model.v \
  129. -v $QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.v \
  130. -v $QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.v \
  131. $QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv \
  132. -v $QUARTUS_INSTALL_DIR/eda/sim_lib/synopsys/cyclonev_atoms_ncrypt.v \
  133. -v $QUARTUS_INSTALL_DIR/eda/sim_lib/synopsys/cyclonev_hmi_atoms_ncrypt.v \
  134. -v $QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_atoms.v \
  135. -v $QUARTUS_INSTALL_DIR/eda/sim_lib/synopsys/cyclonev_hssi_atoms_ncrypt.v \
  136. -v $QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_hssi_atoms.v \
  137. -v $QUARTUS_INSTALL_DIR/eda/sim_lib/synopsys/cyclonev_pcie_hip_atoms_ncrypt.v \
  138. -v $QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_pcie_hip_atoms.v \
  139. $QSYS_SIMDIR/mainpll.vo \
  140. -top $TOP_LEVEL_NAME
  141. # ----------------------------------------
  142. # simulate
  143. if [ $SKIP_SIM -eq 0 ]; then
  144. ./simv $SIM_OPTIONS $USER_DEFINED_SIM_OPTIONS
  145. fi