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mainpll_0002.v 2.3 KB

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  1. `timescale 1ns/10ps
  2. module mainpll_0002(
  3. // interface 'refclk'
  4. input wire refclk,
  5. // interface 'reset'
  6. input wire rst,
  7. // interface 'outclk0'
  8. output wire outclk_0,
  9. // interface 'outclk1'
  10. output wire outclk_1,
  11. // interface 'outclk2'
  12. output wire outclk_2,
  13. // interface 'outclk3'
  14. output wire outclk_3,
  15. // interface 'outclk4'
  16. output wire outclk_4,
  17. // interface 'locked'
  18. output wire locked
  19. );
  20. altera_pll #(
  21. .fractional_vco_multiplier("false"),
  22. .reference_clock_frequency("50.0 MHz"),
  23. .operation_mode("direct"),
  24. .number_of_clocks(5),
  25. .output_clock_frequency0("100.000000 MHz"),
  26. .phase_shift0("0 ps"),
  27. .duty_cycle0(50),
  28. .output_clock_frequency1("100.000000 MHz"),
  29. .phase_shift1("5000 ps"),
  30. .duty_cycle1(50),
  31. .output_clock_frequency2("50.000000 MHz"),
  32. .phase_shift2("0 ps"),
  33. .duty_cycle2(50),
  34. .output_clock_frequency3("25.000000 MHz"),
  35. .phase_shift3("0 ps"),
  36. .duty_cycle3(50),
  37. .output_clock_frequency4("125.000000 MHz"),
  38. .phase_shift4("0 ps"),
  39. .duty_cycle4(50),
  40. .output_clock_frequency5("0 MHz"),
  41. .phase_shift5("0 ps"),
  42. .duty_cycle5(50),
  43. .output_clock_frequency6("0 MHz"),
  44. .phase_shift6("0 ps"),
  45. .duty_cycle6(50),
  46. .output_clock_frequency7("0 MHz"),
  47. .phase_shift7("0 ps"),
  48. .duty_cycle7(50),
  49. .output_clock_frequency8("0 MHz"),
  50. .phase_shift8("0 ps"),
  51. .duty_cycle8(50),
  52. .output_clock_frequency9("0 MHz"),
  53. .phase_shift9("0 ps"),
  54. .duty_cycle9(50),
  55. .output_clock_frequency10("0 MHz"),
  56. .phase_shift10("0 ps"),
  57. .duty_cycle10(50),
  58. .output_clock_frequency11("0 MHz"),
  59. .phase_shift11("0 ps"),
  60. .duty_cycle11(50),
  61. .output_clock_frequency12("0 MHz"),
  62. .phase_shift12("0 ps"),
  63. .duty_cycle12(50),
  64. .output_clock_frequency13("0 MHz"),
  65. .phase_shift13("0 ps"),
  66. .duty_cycle13(50),
  67. .output_clock_frequency14("0 MHz"),
  68. .phase_shift14("0 ps"),
  69. .duty_cycle14(50),
  70. .output_clock_frequency15("0 MHz"),
  71. .phase_shift15("0 ps"),
  72. .duty_cycle15(50),
  73. .output_clock_frequency16("0 MHz"),
  74. .phase_shift16("0 ps"),
  75. .duty_cycle16(50),
  76. .output_clock_frequency17("0 MHz"),
  77. .phase_shift17("0 ps"),
  78. .duty_cycle17(50),
  79. .pll_type("General"),
  80. .pll_subtype("General")
  81. ) altera_pll_i (
  82. .rst (rst),
  83. .outclk ({outclk_4, outclk_3, outclk_2, outclk_1, outclk_0}),
  84. .locked (locked),
  85. .fboutclk ( ),
  86. .fbclk (1'b0),
  87. .refclk (refclk)
  88. );
  89. endmodule