mainpll.cmp 364 B

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  1. component mainpll is
  2. port (
  3. refclk : in std_logic := 'X'; -- clk
  4. rst : in std_logic := 'X'; -- reset
  5. outclk_0 : out std_logic; -- clk
  6. outclk_1 : out std_logic; -- clk
  7. outclk_2 : out std_logic; -- clk
  8. outclk_3 : out std_logic; -- clk
  9. outclk_4 : out std_logic -- clk
  10. );
  11. end component mainpll;