ISA.md 4.4 KB
B32P ISA
The B32P instruction set architecture is a RISC architecture. Each instruction is 32 bits and can be one of the following instructions:
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1 HALT 1 1 1 1| 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
2 READ 1 1 1 0||----------------16 BIT CONSTANT---------------||--A REG---| x x x x |--D REG---|
3 WRITE 1 1 0 1||----------------16 BIT CONSTANT---------------||--A REG---||--B REG---| x x x x
4 INTID 1 1 0 0| x x x x x x x x x x x x x x x x x x x x x x x x |--D REG---|
5 PUSH 1 0 1 1| x x x x x x x x x x x x x x x x x x x x |--B REG---| x x x x
6 POP 1 0 1 0| x x x x x x x x x x x x x x x x x x x x x x x x |--D REG---|
7 JUMP 1 0 0 1||--------------------------------27 BIT CONSTANT--------------------------------||O|
8 JUMPR 1 0 0 0||----------------16 BIT CONSTANT---------------| x x x x |--B REG---| x x x |O|
9 CCACHE 0 1 1 1| x x x x x x x x x x x x x x x x x x x x x x x x x x x x
10 BRANCH 0 1 1 0||----------------16 BIT CONSTANT---------------||--A REG---||--B REG---||-OPCODE||S|
11 SAVPC 0 1 0 1| x x x x x x x x x x x x x x x x x x x x x x x x |--D REG---|
12 RETI 0 1 0 0| x x x x x x x x x x x x x x x x x x x x x x x x x x x x
13 XXX
14 XXX
15 ARITHC 0 0 0 1||--OPCODE--||----------------16 BIT CONSTANT---------------||--A REG---||--D REG---|
16 ARITH 0 0 0 0||--OPCODE--| x x x x x x x x x x x x |--A REG---||--B REG---||--D REG---|
HALT: Will prevent the CPU to go to the next instruction by jumping to the same address. Can be interrupted.READ: Read from memory at address in AREG + (signed) 16 bit offset, store value in DREG.WRITE: Write value from BREG to memory at address stored in AREG + (signed) 16 bit offset.INTID: Store the interrupt ID in DREGPUSH: Pushes value in AREG to stack.POP: Pops value from stack into DREG.JUMP: Set PC to 27 bit constant if O is 0. If O is 1, then add the 27 bit constant to PC.JUMPR: Set PC to BREG + (signed) 16 bit constant if O is 0. If O is 1, then add the value from BREG + (signed) 16 bit constant to PC.CCACHE: Clear all l1 cache by setting all valid bits to 0.BRANCH: Compare AREG to BREG depending on the branch opcode. If S is 1, then used signed comparison. If branch pass, add (signed) 16 bit constant to PC.SAVPC: Save current PC to DREG.RETI: Restore PC after interrupt and re-enable interrupts.XXX: Currently reserved for future instructionsXXX: Currently reserved for future instructionsARITHC: Execute operation specified by OPCODE on AREG and (signed) 16 bit constant. Write result to DREG.ARITH: Execute operation specified by OPCODE on AREG and BREG. Write result to DREG.
BRANCH opcodes
The type of branch operation can be specified by the branch opcode:
Operation|Opcode|Description
-------------------------
BEQ 000 Branch if A == B
BGT 001 Branch if A > B
BGE 010 Branch if A >= B
XXX 011 Reserved
BNE 100 Branch if A != B
BLT 101 Branch if A < B
BLE 110 Branch if A <= B
XXX 111 Reserved
Signed comparisons can be enabled by setting the S (sign) bit, creating the BGTS, BGES, BLTS and BLES operations.
ARITH opcodes
The type of ALU operation can be specified by the ARITH opcode:
Operation|Opcode|Description
-------------------------
OR 0000 A OR B
AND 0001 A AND B
XOR 0010 A XOR B
ADD 0011 A + B
SUB 0100 A - B
SHIFTL 0101 A << B
SHIFTR 0110 A >> B
NOT(A) 0111 ~A
MULTS 1000 A * B (signed)
MULTU 1001 A * B (unsigned)
SLT 1010 1 if A < B, else 0 (signed)
SLTU 1011 1 if A < B, else 0 (unsigned)
LOAD 1100 16 bit constant (or B)
LOADHI 1101 {16 bit constant, A[15:0]} (if AREG == DREG, this is equivalent to LOADHI)
SHIFTRS 1110 A >> B with sign extension
The remaining opcodes are reserved for future operations.