cpu.v 869 B

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  1. module CPU(
  2. input clk, reset,
  3. output [26:0] bus_addr,
  4. output [31:0] bus_data,
  5. output bus_we,
  6. output reg bus_start,
  7. input [31:0] bus_q,
  8. input bus_done, bus_ready,
  9. input clear, hold
  10. );
  11. reg ignoreNext;
  12. reg [31:0] addr = 0;
  13. assign bus_addr = addr;
  14. assign bus_data = 32'd0;
  15. assign bus_we = 1'b0;
  16. always @(posedge clk)
  17. begin
  18. if (reset)
  19. ignoreNext <= 1'b0;
  20. else if (ignoreNext && bus_done)
  21. ignoreNext <= 1'b0;
  22. else if (clear && bus_start)
  23. ignoreNext <= 1'b1;
  24. end
  25. always @(posedge clk)
  26. begin
  27. if (reset)
  28. begin
  29. addr <= 0;
  30. bus_start <= 0;
  31. end
  32. else
  33. begin
  34. if (bus_ready && !hold && !(bus_start && !bus_done))
  35. begin
  36. bus_start <= 1'b1;
  37. addr <= addr + 1;
  38. end
  39. else
  40. bus_start <= 1'b0;
  41. end
  42. end
  43. endmodule