bart/FPGC6 @ bc8abaa28f6c5e2b5a2d9d7e0fb964a340245878

镜像自地址 https://github.com/bartpleiter/FPGC6

bart e1bb01a621 Cleaned and renamed Quartus project.		1 年之前
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RGB2HDMI.v	442d51ba85 Added images to documentation, HDMI is working without lvds, init of new sdram controller done.	2 年之前
TMDSenc.v	b74702c915 Created full FPGC6 verilog simulation, added Quartus code from FPGC5 with CPU from FPGC6. Works in hardware, but has combination loop somewhere at the arbiter and the registerbank and stack are not using block ram	2 年之前