| .. |
|
Bootloaders
|
7e81e7fa17
Added files missing from last commit (L1I cache).
|
1 year ago |
|
SimTests
|
28bcde6466
New SDRAM controller that uses both SDRAM chips. Now separate bus from MU for better performance, as controller runs at 100MHz. Also updated some debug code as debugging was needed. Tested working in hardware. 2x performance boost in some cases.
|
1 year ago |
|
Assembler.py
|
bc8abaa28f
Fixed file permissions, small doc update, create ALU unit test.
|
1 month ago |
|
CompileInstruction.py
|
01a00e1603
Update new repo link, add requirements.txt.
|
8 months ago |
|
buildToVerilog.sh
|
28bcde6466
New SDRAM controller that uses both SDRAM chips. Now separate bus from MU for better performance, as controller runs at 100MHz. Also updated some debug code as debugging was needed. Tested working in hardware. 2x performance boost in some cases.
|
1 year ago |
|
compileAndSend.sh
|
1026f4776c
Cleaned up some files
|
2 years ago |
|
simulate.sh
|
1026f4776c
Cleaned up some files
|
2 years ago |
|
simulateCPU.sh
|
9b3e3a5eb7
Initial progress with faster design.
|
2 months ago |
|
testbus.sh
|
9b3e3a5eb7
Initial progress with faster design.
|
2 months ago |
bartpleiter
bc8abaa28f
Fixed file permissions, small doc update, create ALU unit test.